Tilera has announced the TILE-Gx100, what it claims to be the world's first 100-core processor. The TILE-Gx family -- available with 16, 36, 64, and 100 cores -- employs Tilera's architecture that scales beyond the core count of traditional microprocessors.
"The launch of the TILE-Gx family, including the world's first 100-core microprocessor, ushers in a new era of many-core processing. We believe this next generation of high-core count, ultra high-performance chips will open completely new computing possibilities," said Tilera's Omid Tahernia.
The TILE-Gx family, fabricated in TSMC's 40 nanometer process, operates at up to 1.5 GHz with power consumption ranging from 10 to 55 watts. The TILE-Gx family incorporates many cores on a single chip together with integrated memory controllers and a set of I/O. However the TILE-Gx device also brings together a number of new features to maximize application performance while offering the best performance-per-watt in the industry.
Among the processor's features are:
- New three-issue 64-bit core with full virtual memory system. Each core includes 32KB L1 I-cache, 32KB L1 D-cache and 256KB L2 cache, with up to 26MB total L3 coherent cache across the device.
- Enhanced SIMD instruction extensions: Improved signal processing performance with a 4 MAC/cycle multiplier unit delivering up to 600 billion MACs per second.
- Integrated high-performance DDR3 memory controllers: Two or four 72-bit controllers running up to 2133 MHz speeds with ECC support. Up to 1TB total capacity.
- Hardware acceleration engines: On-chip MiCA (Multistream iMesh Crypto Accelerator) system delivers up to 40Gbps encryption and 20Gbps full duplex compression processing, tightly coupled to the iMesh for extremely low latency and wire-speed small packet throughput. In addition, a high-performance true random number generator (RNG) and public key accelerator enable up to 50,000 RSA handshakes per second.
- Packet processing accelerator: mPIPE (multicore Programmable Intelligent Packet Engine) system provides wire-speed packet classification, load balancing and buffer management. This C-programmable engine delivers 80 Gbps and 120 million packets-per-second of throughput for packets with multiple layers of encapsulation.