Intel has made public details about its upcoming multi-processor servers that are based on Intel's 6-core processor codenamed "Dunnington" and its new Itanium processor codenamed "Tukwila," along with disclosing technical features of its previously announced "Nehalem" and "Larrabee" processors.
Dunnington, the first IA (Intel Architecture) processor with 6-cores, is based on the 45nm high-k process technology, and has large shared caches. It also supports FlexMigration technology, which allows a single compatible virtualization pool that supports live VM (Virtual Machine) migration across both 65nm and 45nm high-k Intel Core microarchitecture-based servers and 45nm-based servers.
Tukwila is Intel's next-generation Itanium processor with four cores, 30MB total cache, QuickPath Interconnect, dual Integrated Memory Controller and mainframe-class RAS features. It is a 2-billion transistor microprocessor and projected to deliver more than double the performance of the current generation Itanium processor.
Nehalem is scalable with future versions having anywhere from 2 to 8 cores, with Simultaneous Multi-threading, resulting in 4- to 16-thread capability. Nehalem will deliver 4 times the memory bandwidth compared to today's highest-performance Intel Xeon processor-based systems. With up to 8 MB level-3 cache, 731 million transistors, Quickpath interconnects (up to 25.6GB per second), integrated memory controller and optional integrated graphics, Nehalem will eventually scale from notebooks to high-performance servers. Other features include support for DDR3-800, 1066, and 1333 memory, SSE4.2 instructions, 32KB instruction cache, 32KB Data Cache, 256K L2 data and instruction low-latency cache per core and new 2-level TLB (Translation Lookaside Buffer) hierarchy.
Larrabee includes a high-performance, wide SIMD vector processing unit (VPU) along with a new set of vector instructions including integer and floating point arithmetic, vector memory operations and conditional instructions. In addition, Larrabee includes a major new hardware coherent cache design enabling the many-core architecture. The architecture and instructions have been designed to deliver performance, energy efficiency and general purpose programmability to meet the demands of visual computing and other workloads that are inherently parallel in nature.
The AVX instruction set will increase performance in floating point, media, and processor-intensive software. AVX can also increase energy efficiency, and is backwards compatible to existing Intel processors. Key features include wider vectors, increasing from 128- to 256-bit wide, resulting in up to 2x peak FLOPs output. Enhanced data rearrangement, resulting in allowing data to be pulled more efficiently, and three operand, non-destructive syntax for a range of benefits.
