Verilog is decidedly schizophrenic. There is part of the Verilog language that synthesizers can commonly convert into FPGA logic and then there is an entire part of the language that doesn't synthesize.
October 07, 2013
URL:http://www.drdobbs.com/cpp/fast-ip-routing-with-lc-tries/cpp/primitive-verilog/240162355
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