The last few weeks, I've been building vtach — a Verilog implementation of CARDIAC, the old paper-based demonstration computer from Bell Labs.
I would like to continue our discussion with a particularly nasty case in which the result is not well defined.
I want to squash a bug as a way to show how you "debug" Verilog hardware designs (or, at least, one way to do so)
Aliasing can cause paradoxical behavior.
I want to talk a bit more about Verilog and how it is different from simply writing something using software.
We can "optimize" our code by removing requests for operations that our data structures do not really need to support.
A paper computer is certainly novel, and the spreadsheet version lets students get familiar with the architecture without having to write on cardboard. I wanted to go further, though.
Kernighan's rule for optimizations (Don't do it) is good advice. But as with most rules, there are exceptions.
FPGAs are great for experimenting with CPU designs.
Use your body's electric field to authenticate