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Gastón Hillar

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Coreinfo v2.0: A Simple Utility to Understand the Manycore Complexity in Windows

October 27, 2009

Windows Server 2008 R2 and Windows 7 (64-bits version) offer new NUMA (Non-Uniform Memory Access) support. Therefore, it is very important for Windows developers to understand the differences found in the complex underlying multicore and manycore hardware. Coreinfo is a very simple yet powerful command-line utility that shows you very useful information about the processors, their organization and the cache topology.A few days ago, Mark Russinovich, a well-known member of Windows Sysinternals team made the new version v2.0 of Coreinfo available for download.

This command-line utility runs on most modern Windows versions and displays information about the mapping between logical cores (logical processors or hardware threads) and the physical cores. Besides, it shows information about the NUMA nodes, groups, sockets and all the cache levels. This information is very important to understand the underlying hardware. When you benchmark multicore performance, the great differences between many multicore architectures can make it really difficult to tune the application for a specific architecture. Using this command-line utility, you can easily save the information about the underlying hardware before running your benchmarks and performance tests.

The new version supports Windows Server 2008 R2 systems with more than 64 logical processors (logical cores or hardware threads). Besides, it is also compatible with IA-64 architectures. You don't need to run an installer. You can unzip the executable file and run it from the command-line.

The utility uses the GetLogicalProcessorInformation Windows API function to obtain all the information displayed on the screen. Therefore, you can also obtain this information in your applications to tune performance according to the underlying hardware architecture. In fact, if you plan to create applications targeting manycore systems with multiple NUMA nodes, you'll have to take into account the detailed cache topology if you want to exploit the underlying hardware.

The results of running Coreinfo v2.0 on an Intel Atom N270 powered netbook are the following: Logical to Physical Processor Map: ** Physical Processor 0 (Hyperthreaded) Logical Processor to Socket Map: ** Socket 0 Logical Processor to NUMA Node Map: ** NUMA Node 0 Logical Processor to Cache Map: ** Data Cache 0, Level 1, 24 KB, Assoc 6, LineSize 64 ** Instruction Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64 ** Unified Cache 0, Level 2, 512 KB, Assoc 8, LineSize 64

There is just one physical core. However, as this CPU offers Hyper-Threading technology, Coreinfo tells you it is Hyperthreaded.

The results of running Coreinfo v2.0 on an Intel Core 2 Duo P8600 powered notebook are the following: Logical to Physical Processor Map: *- Physical Processor 0 -* Physical Processor 1 Logical Processor to Socket Map: ** Socket 0 Logical Processor to NUMA Node Map: ** NUMA Node 0 Logical Processor to Cache Map: *- Data Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64 *- Instruction Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64 -* Data Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64 -* Instruction Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64 ** Unified Cache 0, Level 2, 3 MB, Assoc 12, LineSize 64

Coreinfo uses an asterisk "*" to represent a mapping. In this case, there are two physical cores and two logical cores as there isn't Hyper-Threading technology. Besides, there is a unified 3 MB Level 2 cache memory. Both physical cores share this cache, therefore, Coreinfo shows two asterisks "**" on the left side of the last line. This means that the cache is mapped to both processors: *- =Physical Processor 0 -*=Physical Processor 1

Therefore, ** means Physical Processor 0 and Physical Processor 1.

The results of running Coreinfo v2.0 on an Intel Core 2 Quad Q6600 powered workstation are the following: Logical to Physical Processor Map: *--- Physical Processor 0 -*-- Physical Processor 1 --*- Physical Processor 2 ---* Physical Processor 3 Logical Processor to Socket Map: **** Socket 0 Logical Processor to NUMA Node Map: **** NUMA Node 0 Logical Processor to Cache Map: *--- Data Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64 *--- Instruction Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64 -*-- Data Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64 -*-- Instruction Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64 **-- Unified Cache 0, Level 2, 4 MB, Assoc 16, LineSize 64 --*- Data Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64 --*- Instruction Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64 ---* Data Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64 ---* Instruction Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64 --** Unified Cache 1, Level 2, 4 MB, Assoc 16, LineSize 64 Logical Processor to Group Map: **** Group 0

In this case, there are four physical cores and four logical cores as there isn't Hyper-Threading technology. Besides, there are two unified 4 MB Level 2 cache memories. Each pair of physical cores share this cache, therefore, Coreinfo shows asterisks to identify the processors mapped to each cache: *---=Physical Processor 0 -*--=Physical Processor 1 --*-=Physical Processor 2 ---*=Physical Processor 3

Therefore, **-- means Physical Processor 0 and Physical Processor 1, and --** means Physical Processor 2 and Physical Processor 3.

These are the two lines that display the information about each unified cache mapped to each pair of physical processors: **-- Unified Cache 0, Level 2, 4 MB, Assoc 16, LineSize 64 --** Unified Cache 1, Level 2, 4 MB, Assoc 16, LineSize 64

In the aforementioned examples, there is just one NUMA node. Some of the results of running Coreinfo v2.0 on a server powered by two quad-core AMD Opteron 2379 HE microprocessors with a NUMA architecture are the following: Logical to Physical Processor Map: *

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