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digitcl.txt

Associated article: Hierarchical Logic Simulation

Tags: C/C++         

Published source code accompanying the article by Donald Craig in which presents an approach by which hardware components can be represented and simulated hierarchically using C++. His simulation strategy is completely asynchronous, meaning that the concept of global time has been abandoned in favor of each component maintaining its own concept of local time. Also see DIGITCL.ZIP.

					Hierarchical Logic Simulation
by Donald C. Craig


Figure 2:

Signals values on wire: Main w4
     {_ X} {2 1} {3 0} {5 1} {6 0} 



Listing One
class Component
{
public:
    virtual     ~Component();

    list<Port *>     I_List;
    list<Port *>     O_List;
    virtual void     process(ckt_time);
    void         ...							
										
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