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Al Williams

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Flip Floppy

December 03, 2011

Of course, inputs from the outside world might not be synchronized, but don't worry about that for now. Inputs from other parts of our circuit can easily be synchronized to a single clock and FPGAs have special provisions for handling clock signals.

Typically, a flip flop has two outputs: Q and Q' (often written as a Q with a bar over it). Q' is simply the inverse of the normal output. So if Q=1 then Q'=0 and vice versa. When we build flip flops with Verilog, we can use either output (or both).

There are many common types of flip flops. Perhaps the most common is the D (data) flip flop. In addition to a clock input and the Q outputs, a D flip flop has a single input (named, unsurprisingly, D). When the clock makes the enabled transition, whatever value D has becomes the new Q value. In Verilog:

module d_ff(input clk, input d, output reg q, output q_not);
assign q_not=~q;
always @(posedge clk)
   q=d;
endmodule

This shows a few new Verilog constructs. The always statement is similar to initial. It causes the associated code to execute when its "sensitivity list" is true. In this case, the code (q=d) executes with the clk signal has a positive edge (that is, goes from a 0 to a 1).

You can specify combinatorial logic using always too:

always @(a or b or c)
   y=a&b|~c;

That causes the line of code to execute when a, b, or c changes. You can also just use always with no list to cause something to — no surprise — always execute.

Try writing a test bench for the D flip flop (you can find mine here). Hint: You can generate a clock (using a reg type) like this:

Initial clk=0;   // start clock low
always #1 clk=~clk;  // flip clock every cycle

If you need more than one line of code in the always block you can use begin end. Here's another version of the D flip flop: module d_ff(input clk, input d, output reg q, output reg q_not); always @(posedge clk) begin q=d; q_not=~q; // uh oh end endmodule

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