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Al Williams

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Starts with a V

June 18, 2013

A few weeks ago I spent a good deal of time talking about Verilog — a description language used to design FPGA circuits. However, several people took me to task for not making much mention of the other major language in use for this purpose: VHDL. VHDL (or VHSIC Hardware Description Language — VHSIC stands for Very High Speed Integrated Circuit) is a language that resembles Ada. That shouldn't be surprising, since both languages have a background with the United States Department of Defense.

Like any language, VHDL has its proponents and its detractors. My guess is if you like C, you might prefer Verilog and if you favor Ada or other similar languages, you might find VHDL to your liking. The languages are functionally similar. That is, you describe concurrent behavior and can only use certain language constructs if you expect to infer hardware designs. Both languages support things that are only for simulation and won't translate to an FPGA or other hardware implementation.

VHDL uses three different things to describe a circuit: an entity (think of this as a header file), an architecture (the implementation), and a configuration (bringing together different architectures into a complete system). Here's a simple 8 bit counter:

-- simple up counter
library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;

entity counter is
    port (
        cntout   :out std_logic_vector (7 downto 0);  
        enable :in  std_logic;                      -- Enable count
        clk    :in  std_logic;                      -- Clock
        reset  :in  std_logic                       -- Reset
    );
end entity;

architecture behave of counter is
    signal count :std_logic_vector (7 downto 0);
begin
    process (clk, reset) begin
        if (reset = '1') then
            count <= (others=>'0');
        elsif (rising_edge(clk)) then
            if (enable = '1') then
                count <= count + 1;
            end if;
        end if;
    end process;
    cntout <= count;
end architecture;

The tools from the major vendors will all take VHDL as well as Verilog. The simulator I used, Icarus, won't handle VHDL but a similar open source package, GHDL, will do the same job. As a side note, Icarus will translate Verilog into VHDL.

I'm not going to go into VHDL for now, but thought it would be worth mentioning it. If you want some interesting reading, as well as a nice front end for GHDL, visit freerangefactory.org. You can download their free book on VHDL (which is a pretty good read), a few other books of interest, and the software package Boot (for Linux), which is a front end that bridges your favorite editor, GHDL, and the OpenCores website. If you are using Windows or Mac OS, skip the Boot download and get GHDL from its home webpage.

You don't have to use an HDL to define an FPGA, by the way. There is a lot of interest in translating ordinary computer languages into FPGA code. While this is possible, it is a bit like running source code through a compiler. The result will work, but understanding the output may be a bit difficult. If you want to experiment, you can try a C to Verilog translator online. If you want to read more about that tool, I wrote about it way back in 2011.

I may revisit VHDL at some point in the future, especially if I get enough requests to do so. However, to be honest, I prefer using Verilog on my personal projects. Sometimes I have no choice, though, so I have done a good bit of VHDL and it certainly gets the job done.

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