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Al Williams

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The Spartan Blue CPU in Verilog

August 17, 2010

I used to work for a big semiconductor maker taking apart CPU chips to find out why they failed. When I wanted to learn more about CPU's I found a copy of Caxton Foster's "Computer Architecture" book. This is an older book today, and not up to date on things like RISC pipelines -- it is geared more towards machines like the old HP1000 or DG Nova (both favorites of mine).

Some years back when I wanted to flex my muscles on FPGA development, I decided to recreate the fictional CPU that Foster developed on a Spartan 3 FPGA from Xilinx. My version is called Spartan Blue. Granted, not the most practical project but it was entertaining and I still use it sometimes to help others get started doing serious FPGA development. It is just about the right level of complexity to be hard without being too hard, if that makes sense.

I found a few "bugs" in the original design (which was all logic diagrams, no Verilog or VHDL). I also changed the clock scheme, made some instructions more efficient, and added a lot of new instructions. I deleted some too -- notably the I/O instructions; my machine has memory mapped I/O.

If you'd like to try Blue, its on OpenCores. In addition, there is some documentation (but not too much, so don't get too excited).

Modifications to Blue would make a good class project or just a way to build your Verilog expertise. Although you'll probably want to use the monitor and serial terminal to load programs, I am particularly proud of Spartan Blue's front panel (which has no analog in the original Blue). You can see the front panel in action on .

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