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Looking For The Lost Packets: Part 1


Cristian F. Dumitrescu is a Software Engineer with the Intel Architecture Group.


Packet-processing systems reside within a network node and handle traffic transitioning through that node. Depending on the network's function, a typical system might be an Ethernet bridge or switch in a Local Area Network (LAN) from your home, office, or data center; a Wide Area Network (WAN) gateway, which is a device that connects your LAN network with the access network of your Internet Service Provider (ISP), ensuring the security of the connection; a Base Station, a Radio Network Controller (RNC) or other device from the access network of the mobile phone/wireless broadband network your phone/modem is connected to; an edge router or core router that is part of the Internet backbone; or any other device that handles the network packets as part of a network.

In this two-part article, we examine some of the typical problems engineers face while debugging packet-processing systems. Because of the complexity of these systems, it is imperative that packet-processing systems be designed with debug capabilities from the start. The techniques presented here represent a collection of built-in mechanisms to be provisioned from as early as the design phase to assist the system debugging at runtime, with the purpose of detecting any system errors from the first stages of development and testing. In Part 1, we examine issues related to debugging functional problems. In Part 2, we turn to debugging of stability and performance problems.

The Typical System Under Debugging

Since packet-processing systems are generally complex systems, debugging is not easy. Moreover, they now contain multicore processors with several on-chip and off-chip configurable acceleration engines and hard-wired logic blocks -- all performing under strict real-time requirements to achieve the expected throughput rate for the traffic flows they are designed to support.

The role of these systems is typically to receive packets from the network or the backplane interfaces, map each packet to one of the known connections (packet classification), process the packet in accordance with the connection requirements and return the packet back to the network or the backplane.

One key aspect is that even if the design is processor-centric and you are just writing software on the multicore processor, you have to debug the whole system, not just a single device in isolation.

Figure 1 illustrates a packet-processing system with at least four Gigabit Ethernet ports based on the Intel Xeon Processor 5500 Series. The system consists of two Quad-Core Intel Xeon Processor 5500 Series processors supporting the simultaneous multithreading technology, thus bringing the number of hardware threads in the system to 16. The speed of the Intel QuickPath Interconnect bus is 6.40 GT/s. Each processor supports three channels of DDR3 memory. Each Intel Gigabit ET Quad Port Server Adapter supports four Gigabit Ethernet ports and is connected to the system through the PCI Express Gen2 bus.

Figure 1: Packet-processing system based on two Quad-Core Intel Xeon Processor 5500 Series processors.


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