Dr. Dobb's Go Parallel Blogs http://www.drdobbs.com/ Dr. Dobb's Copyright 2013, United Business Media. en-us How Do Applications Run on a New Micro-Architecture? Intel VTune Amplifier XE 2011 Answers the Question http://www.drdobbs.com/parallel/how-do-applications-run-on-a-new-micro-a/232601968 The Profile System target type provided by Intel VTune Amplifier XE 2011 allows you to analyze the system performance as a whole and provides you with all the information you might need in order to optimize the applications for your new target micro-architecture. Fri, 02 Mar 2012 17:37 EST Getting the Straight Dope on Instruction-Level Optimization http://www.drdobbs.com/parallel/getting-the-straight-dope-on-instruction/232601803 It's not easy to find all the help you need to drop to assembly language optimization or use the latest vector-based instruction extensions, but these resources will help immeasurably. Wed, 29 Feb 2012 18:00 EST Cpuinfo: The Processor Information Utility for Intel MPI Library http://www.drdobbs.com/parallel/cpuinfo-the-processor-information-utilit/232600802 The <code>cpuinfo</code> command-line utility included in the Intel MPI Library is the most convenient tool to gather detailed information about your cluster nodes, their logical processors identifications, the placement on packages, their different cache levels sharing, their feature flags, etc. Tue, 14 Feb 2012 10:46 EST Transactional Synchronization in Haswell http://www.drdobbs.com/parallel/transactional-synchronization-in-haswell/232600598 Intel TSX provides a set of instruction-set extensions that allow programmers to specify regions of code for transactional synchronization Thu, 09 Feb 2012 08:43 EST Intel Cluster Studio XE 2012 and Hybrid MPI/OpenMP Applications: Optimize Up To the Node Level http://www.drdobbs.com/parallel/intel-cluster-studio-xe-2012-and-hybrid/232600105 Intel Cluster Studio XE 2012 provides an MPI hybrid development suite that targets developers on high-performance clusters. Wed, 01 Feb 2012 22:55 EST The CoreInfo 3.03 Utility Provides Detailed Intel Instruction Sets http://www.drdobbs.com/parallel/the-coreinfo-303-utility-provides-detail/232500209 The newest version of CoreInfo provides a detailed summary of all the instructions sets that the CPUs found on the system support. Fri, 20 Jan 2012 13:05 EST Boost Performance for Your Android Native Code http://www.drdobbs.com/mobile/boost-performance-for-your-android-nativ/232300954 The Android NDK is a toolset that lets you embed components that make use of native code in your Android applications. Wed, 21 Dec 2011 20:26 EST Calling IPP Functions from C# Code http://www.drdobbs.com/cpp/calling-ipp-functions-from-c-code/232300486 Intel Integrated Performance Primitives, also known as IPP, is a library of highly optimized math software functions for digital media and data-processing applications. Wed, 14 Dec 2011 10:26 EST Three Parallel Backtracking Designs http://www.drdobbs.com/architecture-and-design/three-parallel-backtracking-designs/232300302 Clay presents three design versions of the parallel <code>NQueens()</code> function. Fri, 09 Dec 2011 18:41 EST Retrieving Detailed Information About Your Intel Multicore CPU Features with Intel IPP http://www.drdobbs.com/tools/retrieving-detailed-information-about-yo/232300050 There are several ways of retrieving detailed information about your Intel multicore CPU features. I discovered two functions in IPP that provide most of the information I usually need. Tue, 06 Dec 2011 20:26 EST Implicit CPU Vectorization with Intel OpenCL SDK 1.5 http://www.drdobbs.com/open-source/implicit-cpu-vectorization-with-intel-op/232200021 Intel OpenCL SDK 1.5 includes important performance enhancements specifically designed for the latest Intel 2<sup>nd</sup> Generation Core Processors and outlines a path for future performance improvements. Tue, 22 Nov 2011 15:15 EST Backtracking for Fun and Profit http://www.drdobbs.com/cpp/backtracking-for-fun-and-profit/232200113 Backtracking can be used to find all (or some) solutions to problems that are able to incrementally build candidates to solutions. Tue, 22 Nov 2011 14:21 EST Intel Vector Statistical Library http://www.drdobbs.com/tools/intel-vector-statistical-library/231903378 Boost performance of pseudo-random and quasi-random number generation Fri, 18 Nov 2011 11:24 EST Rise of the Planet of the Iterative Quicksort http://www.drdobbs.com/cpp/rise-of-the-planet-of-the-iterative-quic/231901513 In the third and final part of the Iterative Quicksort trilogy, anything can happen and anyone can die. Mon, 24 Oct 2011 12:19 EDT Introducing Intel Labs' River Trail http://www.drdobbs.com/web-development/introducing-intel-labs-river-trail/231602396 Getting parallelized functions to work with arrays in JavaScript Thu, 29 Sep 2011 11:00 EDT Parallel Data Structures http://www.drdobbs.com/architecture-and-design/parallel-data-structures/231601211 Fantasy or (yet-to-be-discovered) reality? Mon, 12 Sep 2011 12:12 EDT Parallelism As a First Class Citizen in C and C++ http://www.drdobbs.com/cpp/parallelism-as-a-first-class-citizen-in/231500025 We need mechanisms for parallelism that have strong space-time guarantees, simple program understanding, and serialization semantics &#151; all things we do not have in C and C++ today Tue, 16 Aug 2011 09:57 EDT Intel Vector Math Library http://www.drdobbs.com/tools/intel-vector-math-library/231400052 A simpler way to take advantage of SIMD instructions Thu, 11 Aug 2011 11:13 EDT Memory Constraints on Thread Performance http://www.drdobbs.com/tools/memory-constraints-on-thread-performance/231300494 Threading is no guarantee of improved performance if memory issues are not attended to Tue, 09 Aug 2011 13:08 EDT Introducing Embree http://www.drdobbs.com/tools/introducing-embree/231001621 Open source photo-realistic ray tracing kernels that take full advantage of SSE and AVX on the CPU Wed, 13 Jul 2011 13:57 EDT Intel OpenCL SDK 1.1 http://www.drdobbs.com/tools/intel-opencl-sdk-11/231001335 Optimized performance for Intel architecture processors Mon, 11 Jul 2011 13:59 EDT Intel AVX2 Will Bring Integer Instructions with 256-bit SIMD Numeric Processing Capabilities http://www.drdobbs.com/tools/intel-avx2-will-bring-integer-instructio/231000372 The forthcoming microarchitecture, codenamed "Haswell," will introduce Intel AVX2 in 2013 Fri, 24 Jun 2011 12:57 EDT I'll have An ISO C++ (New Standard Compliant) Compiler with my SPARC T4, Please! http://www.drdobbs.com/cpp/ill-have-an-iso-c-new-standard-compliant/231000186 "Oracle's Five Year Plan for the SPARC T-Series" sparks a sigh of relief Wed, 22 Jun 2011 11:57 EDT Testing and Logical Fault Tolerance for Parallel Programs http://www.drdobbs.com/architecture-and-design/testing-and-logical-fault-tolerance-for/230800196 Regardless of how the list of requirements for a piece of software is generated, the testing process must make sure that the software meets those requirements and that the requirements meet the user's expectations Fri, 17 Jun 2011 20:33 EDT High-Level Programming Languages Should Improve Support for SIMD Instructions http://www.drdobbs.com/tools/high-level-programming-languages-should/230600043 Exposing SIMD units within interpreted languages could simplify programs and unleash floods of untapped processor power Mon, 13 Jun 2011 12:19 EDT