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Al Williams

Dr. Dobb's Bloggers

Paper to FPGA

June 03, 2013

You can see some of the memory configuration screens below, as well as some that are configuring the clock DLL. Of course, you don't have to use the GUI tool, but it does ensure that you are getting exactly what you want and not depending on the tool to infer complex structures like memory from your HDL design.

The online listings contain an asm directory that contains a version of axasm that includes a configuration file for CARDIAC (and, thus, for vtach). Here's the example program I mostly used for testing:

	;;  Test program to debug the BCD math
	ORG 0
	SFT 8,0  		; read switches to AC
	STO 70 			
	OUT 70 			
	SFT 9,0			; read pushbutton (-1 or 1)
	TAC exe			; button down? 
	SFT 0,9			; read other pushbutton
	TAC exe2
	JMP top			
exe:  				; add 1 to count
	LOD 70			
	ADD one			
	STO 70 			
wait:	SFT 9,0			; wait for button up
	TAC wait
	JMP top

exe2:	LOD 70			; decrease count
	SUB one
	STO 70
wait2:	SFT 0,9			; wait for button up
	TAC wait2
	JMP top

one:	DATA 1			; Needed a 1

The program reads the toggle switches and displays the corresponding number of the display (remember, enter numbers in BCD so no digits above 9). If you push PB3, the program increments the number on the display (stored in location 70). Pushing PB1 decrements the number. It isn't much, but it does let you test out the BCD math, which is where I had the most problems.

The core generator lets you set a COE file that contains the program and axasm can generate that. Here's the command line:

axasm –p cardiac –x –o test.coe test.asm

The only catch is you must force the memory core to regenerate every time you change the COE file. You simply select the RAM component in the project hierarchy window and then select "Regenerate Core" from the process window. Then you have to rebuild the project. There are other ways to inject your program into the FPGA-based CPU, but for a simple design like vtach, this is good enough.

When I originally set out to write vtach, I had it in mind for students who wanted to learn more about computer engineering or FPGAs. In retrospect, I'm not sure it would work well for that. While it is simpler than some CPUs, the BCD arithmetic made the design more complicated than I wanted. If I were going to try this with students, I think I'd either switch to binary or, at least, I would provide them with bcdadd.v and all of its component parts along with the I/O modules (unless I was sticking with simulation only).

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