Figure 2. Relative power consumption, clock frequency and silicon area of different video coding hardware architectures in H.264 decoding (VGA@30fps) use case. Hardwired (HW) figures are for ON2 Hantro 7170 HW decoder. DSP platform figures are averages several DSP solutions. ARM performance figures are for ON2 Hantro's 6100 SW decoder. Power consumption estimates are based on use of a general purpose ("G") silicon process.
Optimized DSPs, which utilize less parallelism than a HW solution, also require additional on-chip memory to store interim calculations as well as program code. This increases their total die area requirement relative to HW designs. Typical DSPs, in fact, dedicate more than 60% of their die area to SRAM. Both a HW video codec core in a SoC and a programmable video capable DSP would require approximately 300K gates to implement in logic. However, while a HW video codec would require approximately 20KB of on-chip SRAM for decoding, and 35KB for encoding, a DSP would require approximately 30KB of SRAM for decoding, and 140KB of SRAM for a full duplex solution. DSP memory requirements can be lowered by compromising performance, but this introduces risks, as performance becomes dependent on bus congestion conditions in the end product, which are difficult to predict.
HW solutions can achieve additional power savings by employing clock gating, a power-saving technique used in system-on-chip designs. Clocks can be deactivated for functions when they are not required, thereby reducing their power consumption. Implemented during synthesis, automatic clock gating can achieve up to a 70% reduction in the overall power consumption. Although extremely effective, it cannot reduce the dynamic power consumption of unused blocks to absolute zero because it is unable to de-activate the clock for all of the functions within the block.
For multi-format video codecs, implementing dynamic clock gating can further enhance power consumption. By detecting the formats being used, the feature completely shuts down the blocks reducing their dynamic power consumption to absolute zero. Dynamic clock gating can reduce power consumption an additional 30% after automatic clock gating has been applied.
HD video requires hardwired architecture for mobile handsets
As HDMI interfaces are becoming common in mobile devices, users will be able to display videos on HDTV screens. The processing power requirement of a HD decoder is significantly more demanding than the VGA case presented above, where the absolute clock frequencies are below 50 MHz for a HW codec, in the range 100-200 MHz for DSPs, and about 500 MHz for a RISC core. It is clear that a HW solution is the only viable one for a HD decoder, as all single-core programmable solutions would require clock frequencies of several hundred MHz. Such clock frequencies are too high for low-power, mobile chips. By using a complex multi-core design style, it is possible to develop a DSP-based HD decoder that runs at 200-300 MHz, but the area and power consumption are 200% higher compared to a HW solution.
The real challenge, however, is the HD encoder. User-created content has long ago broken out of the boundaries of tiny mobile phone screens. The driver for mobile phones' video performance requirements today is the size of the screen used to watch videos on computers and HDTV sets. Therefore, VGA or standard-definition video quality will not be acceptable for future handset designs, as users expect image quality that is similar to their phone's multi-megapixel still camera.
A video encoder's computational complexity is more than two times that of the decoder. Referring to the decoder's clock frequency requirements discussed above, it is obvious that only a HW solution is feasible for the encoder. An encoder supporting the 720p resolution can be implemented in a mobile chip even with today's mainstream silicon technology (90 nm CMOS), while 1080p is feasible in 65 nm and 45 nm CMOS technologies. No alternative architectures exist for realizing a complete HD encode-decode solution for mobile handsets.
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