Xilinx provides the Buffer Layer Reference Design as source-code that performs automatic packet re-prioritization and queuing. The SRIO Physical Layer IP implements link training and initialization, discovery and management, and error and retry recovery mechanisms. Additionally, high-speed transceivers are instantiated in the Physical Layer IP to support 1- and 4-lane SRIO bus links at line rates of 1.25Gbps, 2.5Gbps, 3.125Gbps.
A Register Manager reference design enables the SRIO host device to configure and maintain endpoint device configuration, link status, control, and time-out mechanisms. In addition, ports are provided on the Register Manager for the user-design to probe the status of the endpoint device.
LogiCORE provides complete endpoint IP. It has been tested by leading SRIO device vendors. LogiCORE is delivered through the Xilinx CoreGen GUI tool, which allows users to configure the baud-rates and endpoints. It supports extended features like flow-control, re-transmit suppression, doorbell and messaging. This enables the user to create a flexible, scalable and customized SRIO endpoint IP optimized to the needs of the application. Further details can be found at http://www.xilinx.com/rapidio.
Using the varied resources available in most high-performance FPGAs from Xilinx and other vendors, a system designer can easily create and deploy intelligent solutions to harness advantage scenarios like time-to-market, scalability and extensibility, future-proofing, and so forth. Below we outline some system design examples using SRIO and DSP technologies.
A SRIO System Application I: Embedded System
CPU architectures such as the x86 are optimized for general-purpose applications that do not require extensive use of multiplication. In contrast, DSP architectures are optimized for signal-processing operations including filtering, FFTs, vector multiplication and searching, and image or video analysis.
Embedded systems that use CPUs and DSPs can easily be architected to take advantage of both general-purpose and signal processing. An example of such a system is outlined in Figure 6. It features FPGAs, CPUs and DSP architectures.
(Click to enlarge)
Figure 6. CPU-based high-performance DSP sub-system
Serial RapidIO has become the primary data interconnect for high-end DSPs. In x86 CPUs, the primary data interconnect is PCI Express. As shown in Figure 6, FPGAs can easily be deployed for scaling the DSP application, and/or for bridging disparate data interconnect standards like PCI Express and Serial RapidIO.
In the system depicted here, the PCI Express system is hosted by the Root Complex chipset. The SRIO system is hosted by a DSP. The 32/64-bit PCIe address space (base-address) can be intelligently mapped to the 34/66-bit SRIO Address space (base-address). The PCIe application communicates with the Root Complex through Memory or I/O Reads and Writes. These transactions can be easily mapped to SRIO space through I/O operations such as streaming writes, atomic and acknowledged read/write transactions (SWRITEs, ATOMIC, NREADs, NWRITE/NWRITE_Rs).
Designing such bridge functions is easy in Xilinx FPGAs, since the back-end interfaces for the PCI Express and Serial RapidIO endpoint functional blocks are similar. The Packet Queue block can then perform the crossover from PCIe to SRIO or vice-versa to establish the data flow between these two protocol domains.
A SRIO System Application II: DSP processing application
In applications where DSP processing is the primary architectural requirement, the system architecture can be designed as depicted in Figure 7.
(Click to enlarge)
Figure 7. DSP-intensive farms
Xilinx Virtex-5 FPGAs can act as co-processors to other DSP devices in the system. The complete DSP system solution can be scaled easily if SRIO is used as the data interconnect. These solutions can be future-proofed, made extensible, and be supported across multiple form-factors.
If the DSP-intensive application additionally requires fast number-crunching or data processing, such processing can be offloaded to x86 CPUs. Xilinx Virtex-5 FPGAs allow the PCIe sub-system and the SRIO architecture to be bridged to enable efficient offloading of functionality.
A SRIO System Application III: Baseband processing system
With 3G networks maturing rapidly, OEMs are deploying new form-factors to alleviate capacity and coverage problems FPGA-based DSP architectures using SRIO are the ideal solution to such challenges. Legacy DSP systems can also be retargeted to such fast, low-power FPGA-based architectures to harness FPGA's scalability advantage.
In such a system, as depicted in Figure 8, FPGAs can meet the demands of line-rate processing of antenna traffic and also provide connectivity to other system resources through SRIO. Migration of existing legacy DSP applications, which have inherently slow parallel connectivity, is easy thanks to the high speed and bandwidth provided by the Serial RapidIO protocol.
(Click to enlarge)
Figure 8. Baseband processing
Summary:
Serial RapidIO is appearing in a wide array of new applications, largely centered around DSPs in wired and wireless applications. The key advantages of implementing Serial RapidIO in Xilinx devices are:
- Availability of complete SRIO endpoint solution
- Flexibility and scalability to produce different classes of products with the same hardware and software architecture
- Low power with new GTP transceivers and 65nm technologies
- Easy configurability and flexibility through the CoreGen GUI tool
- Proven hardware interoperability with leading industry vendors supporting SRIO connectivity on their devices
- Lower overall system cost by achieving system integration through use of integrated IO blocks like PCIe and TEMAC.
In addition, FPGAs such as Xilinx's Virtex-5 can meet the power, performance and bandwidth requirements of legacy DSP applications. Additional benefits accrue in terms of system integration, due to the availability of functional blocks like Ethernet MACs, endpoint blocks for PCIe functions, processor IP blocks, memory elements and controllers. The exhaustive list of IP Cores that are supported also means that significant overall system cost savings can be realized.
About the author:
NAVNEET RAO is a Connectivity System Architect at Xilinx, Inc. He specializes in High Speed Connectivity Platform solutions for FPGA / ASIC / ASSP technologies, Transceiver technologies, Communication Platform Design, WiMAX / Switch Fabric /Router platform ASICs and Microcontrollers.
Previously he led teams in architecting and designing Transceivers, Switch Fabric ASICs at Mindspeed Technologies (aka Hotrail, Inc). Navneet has excellent experience having worked in product development teams at Philips Semiconductors developing a communication ASICs for basestation platforms and at LSI Logic designing microcontrollers.
Navneet is also an active member in trade associations like FSA, RapidIO, PCI Express, and HyperTransport. He has been an invited speaker at a number of seminars with industry experts including Embedded Systems Conference, ATCA Summit, Linley Group, RapidIO TA, National's Analog by Design.
Navneet has 13 years industry experience after completing his MSEE from Indian Institute of Technology, Kharagpur, India.
