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Booting an Intel Architecture System, Part II: Advanced Initialization

In the first part of this article, I covered hardware power-up issues, processor operating-mode selection, early initialization steps, memory initialization, and application processor initialization. This article — the final installment — shines a light into advanced device initialization, memory-map configuration, and all the other steps required to prepare the hardware for loading the operating system.

Advanced Device Initialization

Advanced initialization follows early initialization, as you might expect. This second stage is focused on device-specific initialization. In a UEFI-based BIOS solution, advanced initialization tasks are also known as DXE and Boot Device Selection (BDS) phases. The following devices must be initialized to enable a system. Not all are applicable to all embedded systems, but the list is prescriptive for most. This list is applies specifically to SOCs (systems on a chip) based on Intel architecture:

  • General purpose I/O (GPIO)
  • Interrupt controller
  • Timers
  • Cache initialization (this could also be accomplished during early initialization)
  • Serial ports, console in/out
  • Clocking and overclocking
  • PCI bus initialization
  • Graphics (optional)
  • Universal Serial Bus (USB)
  • Serial Advanced Technology Attachment (SATA)

General-Purpose I/O: GPIOs are key to platform extensibility. GPIOs can be configured for either input or output, but can also be configured to enable native functionality. Depending on weak or strong pull-up or pull-down resistors, some GPIOs can function as strapping pins that are sampled at reset by the chip-set, and then have a second function during boot-up and at run-time. GPIOs may also act like sideband signals to allow for system wakes.

SOC devices are designed to be used in a large number of configurations. The devices often have more capabilities than the device is capable of exposing on the I/O pins concurrently. That is because multiple functions may be multiplexed to an individual I/O pin. Before the pins are used they must be configured to implement a specific function or serve as general-purpose I/O pins. The system firmware developer must work through 64 to 256 GPIOs and their individual options with the board designer of each platform to ensure that this feature is properly enabled.

Interrupt Controllers: The Intel Architecture supports several different methods of handling interrupts. No matter which method is chosen, all interrupt controllers must be initialized at start-up.

When the Programmable Interrupt Controller (PIC) is the only enabled interrupt device, the system is in PIC mode. This is the simplest mode. All APIC components are bypassed and the system operates in single-thread mode using LINT0. The BIOS must set the IRQs per board configuration for all onboard, integrated, and add-in PCI devices.

The PIC contains two cascaded 8259s with fifteen available IRQs. IRQ2 is not available because it is used to connect the 8259s. On mainstream components, there are eight PIRQ pins supported by the PCH, named PIRQ[A# :H#]. These route PCI interrupts to IRQs of the 8259 PIC. PIRQ[A#:D#] routing is controlled by PIRQ routing registers 60h—63h (D31:F0:Reg 60- 63h). PIRQ[E#:H#] routing is controlled by PIRQ routing registers 68h—6Bh (D31:F0:Reg 68 — 6Bh). This arrangement is illustrated in Figure 1. The PCH also connects the eight PIRQ[A#:H#] pins to eight individual I/O Advanced Programmable Interrupt Controller input pins, as shown in Table 1.

Figure 1: Platform controller hub PIRQ-to-IRQ routing.

Table 1: Platform controller hub PIRQ routing table.

The Local Advanced Programmable Interrupt Controller (LAPIC) is inside the processor. It controls interrupt delivery to the processor. Each LAPIC has its own set of associated registers as well as a Local Vector Table (LVT). The LVT specifies the manner in which the interrupts are delivered to each processor core.

The I/O Advanced Programmable Interrupt Controller (IOxAPIC) is contained in the I/O Controller Hub (ICH) or the I/O Hub (IOH). It expands the number of IRQs available to 24. Each IRQ's entry in the redirection table may be enabled or disabled. The redirection table selects the IDT vector for the associated IRQ. This mode is available only when running in protected mode.

The boot loader typically does not use Message Signaled Interrupts (MSIs) for interrupt handling.

The Interrupt Vector Table (IVT) is located at memory location 0p. It contains 256 interrupt vectors. The IVT is used in real mode. Each 32-bit vector address consists of the CS:IP for the interrupt vector.

The Interrupt Descriptor Table (IDT) contains the exceptions and interrupts in protected mode. There are 256 interrupt vectors, and the exceptions and interrupts are defined in the same locations as in the IVT. Exceptions are routines that handle error conditions such as page faults and general protection Real-mode Interrupt Service Routines (ISRs) communicate information between the boot loader and the OS. For example, INT10h is used for video services such as changing video mode and resolution. Some legacy programs and drivers, assuming these real-mode ISRs are available, call INT routines directly.

Timers: A variety of timers can be employed in an Intel Architecture system:

  • The Programmable Interrupt Timer (PIT) resides in the IOH or ICH and contains the system timer, also referred to as IRQ0.
  • The High Precision Event Timer (HPET) resides in the IOH or ICH. It contains three timers. Typically, the boot loader need not initialize the HPET, and the functionality is used only by the OS.
  • The Real Time Clock (RTC) resides in the IOH or ICH. It contains the system time. These values are contained in CMOS. The RTC also contains a timer that can be used by firmware.
  • The System Management Total Cost of Ownership (TCO) timers reside in the IOH or ICH. They include the Watch Dog Timer (WDT), which can be used to detect system hangs and reset the system.
  • The LAPIC contains a timer that can be used by firmware.

Memory Caching Control: Memory regions that must have different caching behaviors will vary from design to design. In the absence of detailed caching requirements for a platform, the following guidelines provide a safe caching environment for typical systems:

  • Default Cache Rule: Uncached.
  • 00000000-0009FFFF: Write Back.
  • 000A0000-000BFFFF: Write Combined/Uncached
  • 000C0000-000FFFFF: Write Back/Write Protect
  • 00100000-TopOfMemory: Write Back.
  • Top of Memory Segment (TSEG): Cached on newer processors.
  • Graphics Memory: Write Combined or Uncached.
  • Hardware Memory-Mapped I/O: Uncached.

While MTRRs are programmed by the BIOS, Page Attribute Tables (PATs) are used primarily with the OS to control caching down to the page level.

Serial Ports: An RS-232 serial port or UART 16550 is initialized for either run-time or debug solutions. Unlike USB ports, which require considerable initialization and a large software stack, serial ports have a minimal register-level interface requirements. A serial port can be enabled very early in POST to provide serial output support.

Console In/Console Out: During the DXE portion of the UEFI phase, the boot services include console in and console out protocols.

Clock and Overclock Programming: Depending on the clocking solution of the platform, the BIOS may have to enable the clocking of the system. It is possible that a subsystem such as the ME or a server platform's Baseboard Management Controller (BMC) has this responsibility. It is also possible that beyond the basic clock programming, there are expanded configuration options for overclocking, such as:

  • Based on enumeration, enable or disable clock-output enables.
  • Adjust clock spread settings. Enable, disable, and adjust amount. Note that settings are provided as fixed register values determined from expected usages.
  • Under-clock CPU for adaptive clocking support.
  • Lock out clock registers prior to transitioning to host OS.

PCI Device Enumeration: PCI device enumeration is a generic term that refers to detecting and assigning resources to PCI-compliant devices in the system. The discovery process assigns the resources needed by each device, including the following:

  • Memory, prefetchable memory, I/O space.
  • Memory mapped I/O space.
  • IRQ assignment.
  • Expansion ROM detection and execution.

PCI device discovery applies to all newer interfaces such as PCIe root ports, USB controllers, SATA controllers, audio controllers, LAN controllers, and various add-in devices. These newer interfaces all comply with the PCI specification.

It is interesting to note that in UEFI-compliant systems, it is not during the DXE phase but during BDS that most required drivers are loaded.

Graphics Initialization: The video BIOS or Graphics Output Protocol (GOP) UEFI driver is normally the first option ROM to be executed. Once the main console-out is up and running, the console-in line can be configured.

Input Devices: Refer to schematics to determine which I/O devices are in the system. Typically, a system will contain one or more of the following devices:

  • Embedded Controller (EC): An EC is typically used in mobile or low-power systems. The EC contains separate firmware that controls power-management functions as well as PS/2 keyboard functionality.
  • Super I/O (SIO): An SIO typically controls the PS/2, serial, and parallel interfaces. Most systems still support some of the legacy interfaces.
  • Legacy-Free Systems: Legacy-free systems use USB as the input device. If pre-OS keyboard support is required, then the legacy keyboard interfaces must be trapped. Refer to the IOH/ICH BIOS Specification for more details on legacy-free systems.

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