Artisan Software Tools has announced the first technology solution to emerge from the European Union's Framework7 SATURN project -- a UML/SysML-based hardware/software co-design environment based on Artisan Studio.
Developed in conjunction with the University of Paderborn (Germany), the UML/SysML-based hardware/software co-design solution utilizes an enhanced SysML profile linked to a SystemC code generator for Artisan Studio. This generates executable SystemC which is then translated into VHDL for execution in an FPGA. The generated code can also be used to simulate systems in the Artisan EXITE ACE environment, including hardware simulation. This co-design and code generation solution has been fully evaluated using two complex, industrial proof-of-concept cases studies -- a smart camera system and an outdoor broadband wireless telecommunications system. These initial case studies resulted in 56% and 58% automatic code generation respectively, with the simulation behaving as the final FPGA implementation.
"By bridging the gap between modeling, verification and synthesis, of hardware and software in UML/SysML-based designs, SATURN will demonstrate a significant reduction in time-to-market for embedded systems," said Paul Whiston, Project Manager for Artisan Software Tools. "This is being delivered through the combination of SysML and MARTE as a platform to integrate these models with a run-time environment for cross-domain verification as well as the automatic generation of both hardware (SystemC) and embedded software (C/C++) components. The integration of these different abstraction layers will allow seamless integration at functional and target architecture levels. At this mid-point in the project we have delivered an initial version of the complete tool chain, from design to implementation on the target hardware with optional simulation."
This first phase of the project concentrated on hardware (FPGA) modeling. In the next phase, the environment will be expanded to offer target processor simulation for software and the simulation of the SystemC in the EXITE ACE environment. The project will also use the MARTE profile for Formal System Design (ForSyDE), and develop a HetSC profile in conjunction with the University of Cantabria which will aid formal verification of developed systems. This will be evaluated using proof-of-concept case studies and is expected later in 2010.
Started in January 2008, the SATURN (SysML bAsed modeling, architecTUre exploRation, simulation and syNthesis for complex embedded systems) project is a European Union 7th Framework Program initiative. SATURN's objective is to bridge the current gap between modeling and verification/synthesis in UML/SysML-based embedded systems designs that are equally composed of hardware and software. To do this, the OMG's UML profile for MARTE is being evaluated for its complementary application with SysML, and significantly improved adding formal semantics of different Models of Computation for integrated modeling and verification environments. The project will cost 3.75M to execute across all partners with a contribution from the EU of 2.45M.