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Al Williams

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3D FPGAs

April 08, 2010

It seems that every few years 3D movies make a come back. Creature from the Black Lagoon -- that was the first movie I ever saw in 3D. The last one I saw was Avatar. Quite a difference. Lately there's been talk of 3D ICs -- stacking multiple dice in one package.

A start up company called TierLogic may have an early form of this type of IC available. Its not exactly what most people mean by 3D, but its still a step and a very interesting step at that.

Normal FPGAs work by having RAM memory that stores configuration bits. When the chip powers up, an external source (like a EEPROM) loads the RAM memory and the configuration bits make connections between different parts of the chip. That's an oversimplification, but its close enough.

Where TierLogic differs is that it places the configuration RAM in a layer above the normal FPGA die. That means all of the FPGA die is used for logic and interconnect and none is consumed with configuration RAM.

As an end user, who cares? Presumably a smaller die can have more equivalent gates because of the absence of configuration RAM on the main die (assuming the process to put the RAM layer on doesn't cause too many duds). However, there's another interesting twist if you are producing anything in even moderate volumes. TierLogic can take a device before the RAM is built on top of the die and place in a metal interconnect layer instead.

This gives you a true ASIC very rapidly. Because the underlying FPGA fabric is exactly the same, TierLogic claims that timing and everything else on the new device will be exactly the same regardless of the use of RAM or the use of the metal layer. So--in theory--you can prototype with the TierASIC FPGA and then very easily convert to an ASIC (which requires no configuration and is more tamper-proof than an FPGA).

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