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Al Williams

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May 26, 2013

The Digilent board has a 50MHz clock onboard and the Xilinx tools let you build a clock manager component. I used this to divide the clock by 2 so that the CPU runs at 25MHz. With the four subcycles, that's still over 6MIPS, which is a big upgrade from manually running the CPU on paper! The memory, however, I still run at 50MHz so that the CPU doesn't have to wait for memory transactions to complete.

For the input and output, I robbed one of my old CPUs, Blue. I took the display component and the switch debouncing components. I tweaked the display a bit so it would handle negative numbers. The io_input and io_output files had to change to use these new components. I made the input instruction read the 8 toggle switches on the board (you'd have to devise software means to load all three digits). Also, it is up to you to not enter values beyond 9 on the toggle switches. You've been warned!

I also modified the shift instruction in the ALU. It doesn't make sense to shift the accumulator more than 4 places, so that leaves a few spare slots to add instructions. The opcode 480 reads the toggle switches to the accumulator. The instructions 490, 408, and 409 read one of the three pushbuttons (through a debouncing circuit). If the button is down, the accumulator will contain -1 (perfect for use with the TAC instruction). If the button is not pressed, the accumulator will contain 1.

As I mentioned, I also modified memory.v to use a Xilinx-provided memory primitive. The core generator lets you set parameters using a GUI and create custom components of many types. This wasn't strictly necessary as the software can usually guess when you are building memory and automatically set it up. However, if you use the core generator, you can take control of all the details. You can also specify a COE file that contains the contents of the memory.

The axasm assembler can generate COE files. So to program VTACH, you can generate a COE, regenerate the memory core, and the reconfigure the FPGA. There are other ways you could that too, but for a small design like VTACH, this is quick and easy.

One tricky part to the memory is the fact that VTACH uses BCD numbers and the memory expects a normal binary address. Of course, I could have just created extra memory and wasted cells, but that didn't seem right. Instead, I had memory.v calculate the binary number:

'timescale 1us/1us
// Bit 12 is sign, Bits 11-0 are BCD data
module memory(input clk,input [7:0]memaddr, inout [12:0] dbus, input memoe, input memwrite);

	wire [6:0] binaddress;
   wire [12:0] outdata;   // current output word

// Drive DBUS when asked
   assign dbus=memoe?outdata:13'bz;
// convert BCD address to binary
// binaddress=10*digit1 + digit 0 
//  or 8*digit1+2*digit1+digit0
	assign binaddress=({3'b0, 
          memaddr[7:4]}<<3)+({3'b0, memaddr[7:4]}<<1)+{ 3'b0, memaddr[3:0]};

mainmem ram (
  .clka(clk), // input clka
  .wea(memwrite), // input [0 : 0] wea
  .addra(binaddress), // input [6 : 0] addra
  .dina(dbus), // input [12 : 0] dina
  .douta(outdata) // output [12 : 0] douta


The key is this line:

assign binaddress=({3'b0, 
          memaddr[7:4]}<<3)+({3'b0, memaddr[7:4]}<<1)+{ 3'b0, memaddr[3:0]};

Of course, memaddr[7:4] is the top BCD digit and memaddr[3:0] is the bottom one. Shifting the digit three places to the left is the same as multiplying by 8. Shifting one place multiplies the same digit by 2. Because 8x+2x=10x, this is an easy way to convert the BCD number (you also have to add the bottom digit, as you can see in the code).

I still have a bug or two to work out as I've moved to the hardware. Some of it is in the new code. Some of the bugs were there all along, but now that it is easy to write test software, more of them are coming to light. In addition, the Xilinx Verilog parser provides a lot of warnings that Icarus does not, so I had to clean up a few more things. Since I'm not as bug free as I would like, I won't post all the listings this time, but will wait for next time.

I'm also not going step-by-step on the Xilinx tools. There are great tutorials for that on the Xilinx site and elsewhere. However, if you want to get ready for next time, grab the WebPack ISE and work the tutorials. You don't have to have the hardware to get a feel for it (since it can simulate at least as well as Icarus), but it is more fun if you have the hardware too.

If I do retool this for use with students, I may abandon the BCD approach. Nearly all the trouble I've had to chase down with the design has somehow been related to using BCD. For now, though, I'll stay true to CARDIAC and keep hammering at the pesky BCD code.

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