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Al Williams

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Crystal Logic

October 30, 2011

We live in a world where you use radio every day. Cell phones, HDTVs, and wireless internet connections are all sophisticated radio receivers. Even a "regular" FM radio now has multichannel stereo, digital information, and signal processing. However, very few people learned about radios by jumping right into things quite that sophisticated. In fact, many people who would go on to design high-tech radios started out with something simple like a crystal radio. Perhaps you've made one of these as a kid. It is pretty easy to do (click here, for example).

A crystal radio receiver is a far cry from an HDTV. But the basic principles are the same. You have to walk before you run, and crawl before you can walk. Building a crystal radio is to an HDTV as crawling is to, say, flying a jet plane.

One of the things I have been very interested in over the last decade or so is programmable logic devices (Field Programmable Gate Arrays, or FPGAs, and similar devices). Not surprising since I have a history of working with electronics. I've noticed that recently more and more people are interested in (or at least asking me about) FPGAs and related technology. The idea is you have an IC that contains a bunch of logic gates and a way to "wire them up". So by wiring them one way, the IC can function as a CPU. Wired another way, it can be an alarm controller. Think of it as a box of children's building blocks. It's just a bunch of parts until you put it together in some way.

I've written about these for Dr. Dobb's before. I wanted to take a fresh look, in a crystal radio kind of way, at what's available and why you care. I like to design strange and novel CPU architectures, but that's not really a crystal radio, so my goal is to start small and work up towards something with a little more complexity. What I don't want to do is dive into some deep theory about building a CPU to rival the latest from Intel or AMD. That's the jet plane.

The first thing you might ask is why bother? This is especially true if you skim the Internet looking for things that people have done with programmable logic. A lot of projects you'll see are really better candidates for just using a regular CPU and some software. Not that you can't do things like build a Pong game in an FPGA. After all, you can build a whole CPU in an FPGA, so presumably anything a CPU can do, you can do in an FPGA. But why would you?

The real value to using an FPGA is when you need something either very fast or highly parallel. Consider a CPU. I can easily write a piece of software that emulates one CPU on another. But, of course, it is going to be slower. Every instruction in the target machine will take multiple instructions on the host CPU, so the target will run at a small fraction of the host's clock speed. If you want to run as fast as you can at a given clock speed, building the CPU in an FPGA is the way to go.

Parallel operations are the other strong point to these devices. Imagine I am controlling an industrial process and I need to sample 8 inputs. If any input is greater than a threshold value, I want to shut down

the process. My C code might look like this:

  for (i=0;i<7;i++) {
     v=read_value(i);
     if (v>threshold[i]) emergency_stop();
    }

Even the best C compiler on the fastest processor available is going to take some finite number of instructions (and time) to process this loop. The worst-case time will depend on how many values you have to sample. If you were reading, say, 64 values, the time between samples will go up.

In hardware, I don't have to do things one at a time. I'd build a circuit to compare each value and then the delay would be very short and fixed no matter how many things I have to sample. So for my first input I might write (in Verilog):

assign emergency_stop=emergencystop1 | emergency stop2 | ....;
assign emergency_stop1=value1>threshold1;

That would generate connections to do the test logic in hardware. I could add as many lines like this as I wanted until I ran out of building blocks on the chip. The time between the value going over the threshold and the stop signal going high would be very small and would not significantly depend on how many values I compared (there could be a very small delay change as I make the first line longer, but it would not jump up with every extra input).

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