Q-format is a technique for tracking the relative location of the radix point within arithmetic input and operation results. This is important since certain operations such as multiplication can shift the location of the radix point in the operation result.
The Q-format indicates the location of the radix point within a fixed length word by indicating how many bits are to the right and to the left of the radix point. Thus a signed 16 bit fractional number where the MSB indicates both sign and the integer portion of the numerical value (which must always remain zero for maximum resolution fixed point signed binary fractional numeric representation) with the 15 remaining bits representing fractional values could be represented as Q1.15. Since the word length is fixed and usually 16 bits the traditional representation for this format is Q15.
Multiplication of two Q15 words results in a Q30 value. Implied in the Q30 notation is a 32 bit length word. Q30 thus represents 2 bits of sign and 30 bits of fractional content. The MSB in a Q30 value is called an extended sign bit. Since numbers must eventually be stored as 16 bit words the Q30 number must be stored in Q15 format. Shifting the data right by 15 bits and storing the lower 16 bits of the 32 bit register value effectively converts a Q30 number to a Q15 number. The conversion can also be implemented by shifting the data left by one bit and storing the upper 16 bits of the 32 bit register value. Both of these conversions eliminate the redundant extended sign bit and maintain as many significant information bits as possible (15 in this case).
Finite Word Length Effects
Since DSP data must be represented by fixed point values with a finite number of bits there are differences between an ideal (infinite precision) DSP system's performance and a real world fixed point system.
System error sources can include:
- Register overflow, or protected mode register saturation
- Arithmetic errors (ex: feedback path error gain)
- Coefficient representation errors (ex: coefficient accuracy truncation)
While ADC quantization effects add initial noise (signal inaccuracy or degradation) to a fixed point DSP implementation finite word length effects add additional noise sources to the system. Primary quantization-related sources of finite word length effects include:
- Errors in arithmetic within the algorithm implementation (fixed point truncation)
- Truncation error when results are stored (most DSP processors have extended registers for holding arithmetic operation results, however truncation still occurs when results are stored to memory)
- Quantization of filter coefficients which must be stored in memory.
The effects of quantization are non linear, this results in signal dependent errors which prevent error analysis based on statistical random noise effects.
Finite Word Length Effect Reduction
Using a fixed point DSP processor the potential maximum data magnitude through operation chains must be compared to the maximum numeric representation magnitude and adjusted to reduce or prevent error sources.
When problem areas are identified (via analysis, simulation, emulation or testing) there are a few corrective actions which can be taken:
- Scale the input values and or coefficients
- Select an equivalent or alternative architecture
- Take advantage of DSP processor architecture features
- Implement suspect calculation blocks with saturating arithmetic
The simplest correction method is scaling. Scaling can be applied to certain types of algorithms including filters. The pre-scaling is done before an operation block and then post-scaling is done after the operation block to bring the data back to its original magnitude. The easiest way to scale a value is to shift the data. As discussed previously shifts of one position to the right or left are equivalent of multiplication or division respectively.
If the input data to an operational block must be scaled the coefficients which operate on the data must also be scaled by an equal factor. Determining the minimum amount to down-scale a calculation chain can be challenging. Some signal processors contain saturation aware instructions which will indicate if an overflow condition has occurred. Monitoring the overflow flag while running typical (or maximum) data through the system should help establish a bound on the required scaling range.
It is also possible to simulate the algorithm implementation or run analysis with a tool such as Matlab to determine the correct scaling factor.
Another finite word length effect reduction can be implemented by taking advantage of the fact that DSP processors typically have extended precision internal registers (double precision plus some number of "guard" bits) for holding arithmetic operation results. To take advantage of this architecture feature calculation results should be left in this extended precision format until it is necessary to truncate and save the values.
Yet another finite word length effect reduction can be achieved by implementing an alternative algorithm architecture or form. IIR filters for example have a wide variety of forms with similar theoretical results, but different architectures and real-world error characteristics.
