The IEEE has ratified the IEEE 1149.7 test and debug standard which is intended to expand upon IEEE 1149.1 (JTAG) functionality. Developed in an IEEE working group (WG) led by Texas Instruments Incorporated (TI), IEEE 1149.7 enables manufacturers to accomplish more while using fewer resources. The new standard deploys an adaptable framework which facilitates customization for testing and debugging of a wide array of technologies, including highly pin/package-constrained devices such as consumer electronics and mobile communications. By maintaining backwards-compatibility and leveraging proven tools and infrastructures, IEEE 1149.7 also upholds substantial industry investment in earlier IEEE 1149.x standards.
"IEEE 1149.7 offers a flexible, dynamic solution for designers and engineers contending with shifting design paradigms without eroding the firm foundation established by earlier standards, such as IEEE 1149.1," said Stephen Lau, emulation technology product manager, Texas Instruments. "The combination of an extraordinary level of customizability with already-proven technologies maximizes IEEE 1149.7's effectiveness, ensuring its role as an essential, cost-effective test and debug tool."
The new IEEE 1149.7 standard offers a host of new features and upgrades aimed at addressing unique challenges, such as complex digital circuitry, form factor size constraints, and multiple CPUs, posed by today's smaller, next-generation consumer electronics. The six classes (T0-T5) contained within the standard include IEEE 1149.1 extensions, assuring compliance for chips with multiple TAPs. Other new features and enhanced functionality include:
- Significantly decreased scan chain lengths
- Well-defined power control functions, including four selectable power modes
- Support for two-pin operation, instruction, and custom pin usage
- New test tools such as chip bypass and star topology testing
- Increased port efficiency
- Background data transfers concurrent with advanced scan transactions