Processor Interface Overview
Generally targeted at applications requiring heavy I/O loads, DSPs commonly provide developers with a variety of integrated interfaces—some standard and some proprietary. For example, Blackfin processors from Analog Devices are convergent processors, which means they integrate DSP and MCU functionality into a single device. Blackfin processors have two main types of serial interfaces relevant to audio applications. The processor's low bit-rate TWI (two wire interface) and SPI (serial peripheral interface) modules are used for control and configuration of audio devices. The forward channel of these peripherals is generally used to configure or control audio converters, and the reverse channel relays feedback or status information from the converters. The processor's higher bit rate SPORT (serial port) peripheral is customarily used to perform the actual interchange of audio data.
Blackfin's TWI is compatible with the Philips bidirectional open-collector I²C (Inter-Integrated Circuit) bus. It provides a very simple and concise way to exchange control and data information between multiple devices. It supports both master and slave operation with transmission speeds up to 400 kbits per second. The I²C bus serial data (SDA) and serial clock (SCL) lines (see Figure 1) comprise a multi-master interface, so it can connect to more than one IC capable of initiating a data transfer. The phase differences between the SDA and SCL data streams determine the mode of operation, slave or master, at a given point in time. To list all the world's I²C devices here would be impossible, but suffice it to say that using a DSP with an I²C port opens the architecture up to a very wide variety of interconnectivity options.
1. Example I²C signaling (adapted from Philips spec)
The full-duplex Blackfin SPI is compatible with the Motorola SPI standard. It It operates at up to 33 Mbits per second, well beyond the control needs of most A/D and D/A converters. The SPI name was created by Motorola but is also known as Microwire, which is a trademark of National Semiconductor. Extensions to SPI, including QSPI (Queued Serial Peripheral Interface) and MicrowirePLUS, have also come to market. The SPI consists of a three-pin data communication interface (see Figure 2) that supports both master-slave and multi-master environments. The SPI pins include the MOSI (master output to slave device), the MISO (master input from slave device), and the SCK (serial clock). There are also a total of eight SPI chip-select pins. One input pin lets other SPI devices select the Blackfin processor, and seven output pins let the Blackfin processor select other SPI devices. While developers typically utilize SPI as a synchronous serial communication interface between processors and peripherals, SPI can just as well be used for interprocessor communication. As with I²C, SPI has been widely adopted throughout the industry, and the list of SPI-compatible devices is richly populated.
2. Example SPI signaling
Blackfin's full-duplex synchronous serial port, called "SPORT," operates at high bit rates and supports simultaneous transmit and receive applications. SPORT features that are relevant to audio applications include two sets of independent transmit and receive pins (primary data, secondary data, clock and frame sync). These pins enable eight channels of I²S stereo audio. (I²S is Phillips Semiconductor's "Integrated Interchip Sound" bus protocol for digital audio.), Each of these channels supports word lengths up to 32 bits, surpassing the resolution of most high-precision audio applications.
I²S is a well known serial-bus stereo audio transmission standard, widely used to interconnect system elements like analog-to-digital and digital-to-analog converters. I²S interfaces are also found on some high-end CD and DVD players, and on some PC sound cards. An I²S bus design consists of three serial bus lines: a line with two time-division multiplexing (TDM) data channels, a word select line, and a clock line. In the I²S format (see Figure 3), any device can act as the system master by providing the necessary clock signals, and an I²S slave will usually derive its internal clock signal from an external clock input. The I²S design handles audio data separately from clock signals, and by separating the data and clock signals, time-related errors that can introduce jitter are mitigated, eliminating the need for anti-jitter devices.
3. Example I²S audio signaling