There's nothing special about the order of the parameters, any more than a C function call's parameters matter to the compiler. You simply have to match their order when you use them. But don't think of a module as a subroutine. Think of it as an electronic black box.
Here's the function I want my black box to perform written in C (note that inputs and outputs — at least the way I wrote them above — are one-bit wide):
y=(in1 & in2) & in3;
The truth is, I could write one line of Verilog to capture this:
assign y=(in1 & in2) & in3; // parenthesis not necessary here
assign statement effectively says: Every time
in3 changes, compute this expression and assign it to
y. That's different than in C. In C, the compiler will generate code that computes
y one time with the current values of the inputs. In Verilog, a synthesizer creates an
AND gate that constantly monitors the inputs and produces an output.
However, I said I wanted to use two 2-input
AND gates, so let's use another method to generate an
AND gate (you'd rarely use both methods in one module, other than in an example like this):
module and_test(output y, input in1, input in2, input in3); wire temp; assign y=temp & in3; and(temp,in1,in2); endmodule
assign statement is the same as before, but this time it uses a "wire" (which is just a one-bit variable, sort of). In C, this would be a problem because we didn't set
temp to anything yet. But this isn't C! What sets
temp is the
and gate on the line below.
and() module is built into Verilog and, like a C
printf, can take any number of arguments. So the whole module could be:
and(y,in1,in2,in3). Well, you still need the
module statement and the
endmodule statement, but you know what I mean.
The logical operators are what you expect from C:
& (AND), | (OR), ~ (NOT), and
^, (XOR). You can also use
and, or, nor, xor, nana, xnor, and
not as primitive gates.
and_test module is ready to synthesize or use in another module. Next time I'll show you how you might write a test bench to check out the module and examine the signals during simulation.