If you read this blog with any regularity you probably know I have a thing for designing CPUs to run on FPGAs. I also enjoy Forth now and then.

Here's a pretty simple CPU that runs practically native Forth. That's not exactly a new idea, of course, but I was impressed that the CPU is about 200 lines of Verilog. Although you could wish for more comments, this wouldn't be a bad start for someone who wanted to get their feet wet in CPU design on FPGAs. Its more substantial than some of the really small CPUs, but not as large as some (like my own One-Der).

The author claims the J1 can have a complete system with TCP/IP stack in about 8K bytes and runs at 100 MIPS. Or you can load up an XESS board with it and play Space Invaders if you prefer.