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Engineering Parallel Applications with Tunable Architectures



Current multicore computers differ significantly in hardware characteristics. Software developers therefore hand-tune parallel programs for a given platform to achieve best performance. This is tedious and leads to non-portable code. Although the architecture of parallel applications also requires adaptation to achieve best performance, it is rarely modified because of the additional effort.

In this presentation, Walter F. Tichy of the Karlsruhe Institute of Technology presents the Tunable Architectures approach which proposes to automate the architecture adaptation of parallel programs and uses an auto-tuner to find the best-performing architectural choice for a given machine. Tichy introduces a new architecture description language based on parallel patterns and a framework for expressing architecture variants in a generic way. Several case studies demonstrate significant performance improvements due to automatic architecture tuning and show the applicability of our approach to industrial applications.

Walter F. Tichy is a professor of Computer Science at the Karlsruhe Institute of Technology (formerly University Karlsruhe), Germany. Previously, he was senior scientist at Carnegie Group in Pittsburgh, Pennsylvania and served six years on the faculty of Computer Science at Purdue University. He earned a M.S. and a PhD degree in Computer Science at Carnegie Mellon University in 1976 and 1980, resp. He is director at the Forschungszentrum Informatik, a technology transfer institute in Karlsruhe. He is co-founder of ParTec, a company specializing in cluster computing. His primary research interests are software engineering and parallelism. Prof. Tichy has worked with a number of parallel machines, beginning with C.mmp in the 1970s. In the 1990s, he and his students developed Parastation, a communication and management software for computer clusters that made it onto the Top500 list of the world's fastest computers several times (rank 13 as of Nov. 2009). Now that multicore chips make parallel computing available to everyone, he is researching tools and methods to simplify the engineering of general-purpose, parallel software.

This presentation will be be on Wednesday, February 24, 2010 at 4:00 PM (Central Time). Live video streaming (activated at time of event) is available at http://media.cs.uiuc.edu/live/upcrc0910/.asx.


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