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Optimizing Pixomatic For Modern x86 Processors: Part II

September, 2004: Optimizing Pixomatic For Modern x86 Processors: Part II

EAX Scratch register
EBX Scanline length
ECX 1/z
EDX Scratch register
ESI Pixel-buffer pixel address
EBP Span list pointer
EDI Z-buffer pixel address
ESP Stack pointer
MM0 Previous span (u0, v0)
MM1 Previous span (u1, v1)
MM2 Gouraud GB components
MM3 Gouraud AR components
MM4 Specular GB components
MM5-MM7 Scratch registers
XMM0 1/w
XMM1 u0,v0,u1,v1
XMM2 1/w2
XMM3 Left edge 1/w2
XMM4 Left edge 1/w
XMM5 Left edge u0, v0, u1, v1
XMM6-XMM7 Scratch registers

Table 2: Span generation register allocation.

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