Hal is a hardware engineer who sometimes programs. He is the former editor of DTACK Grounded, and can be contacted at [email protected]/.
In my ample spare time, I've been following the comp.sys.IBM.PC.hardware.chips Newsgroup, and been surprised at the number of critics who don't like Intel's (presumably) proprietary Socket 8 (Pentium Pro) and Slot 1 (Pentium II). "It's unfair," they cry, "to prevent AMD and Cyrix from selling competing CPUs into those sockets!"
I thought you might like some background on what the fuss is about.
The Pentium Pro Bus Circa 1979
Yes, 1979. No, that's not a misprint. That's the year the P896 backplane-bus committee, organized and chaired by Andrew Allison, set up shop and gained IEEE authorization to define Futurebus. The computer community had decided that future high-performance systems would be based on shared-memory multiprocessors, where each processor would have its own cache. And that's a problem.
Since each cache may have a copy of a particular piece of the shared memory, it's important that each cache contain the latest copy. This is called the "cache-coherency problem." Futurebus was designed to include the special bus signals and bus protocols to solve the coherency problem.
Another thing you get with multiple processors and a single shared memory is several devices all simultaneously trying to access that single memory. A method was needed to prioritize and queue the accesses. Futurebus therefore uses a "split-transaction" bus protocol. That means the request for a transaction is prioritized and either rejected or queued. (If the request is rejected, it has to be resubmitted. One of the tricky parts is to assure that the lowest-priority requester doesn't get completely frozen out.) The transaction (typically a memory read or write) generally didn't immediately follow the request.
In a regular computer bus, a memory access request is directly followed by the memory access. The complete transaction is in two parts, and the time required for the transaction is the sum of the two parts. But with a split-transaction bus, where the two parts are separate, requests can proceed in parallel with accesses. For a given memory system speed, this significantly increases the data bus bandwidth.
The Futurebus committee voted to approve a final draft in December 1981, just after shipments of the IBM PC began. But the vote was overturned by the higher Microprocessor Standards committee, and Allison resigned in disgust. As he told me, "It's time to market, Stupid!" After a six-year delay, a revised Futurebus was approved as IEEE 896.1-1987.
Albeit late, the 1987 Futurebus standard was a wonderful improvement over older, simpler busses such as VME and Multibus (I and II). Everybody in the industry agreed that it was a bus for the future, not for the present. (As far as I know, the only use Futurebus saw was as the basis for Ruggedbus, IEEE P1496, which nobody ever used either, at least to a commercially noticeable degree.)
Meanwhile, Back at the Ranch
As the Futurebus committee convened, Intel was in the early stages of defining the most magnificent, grotesque, Brobdingnagian and Byzantine microprocessor of all time. Every cockamamie scheme ever conceived by a wild-eyed computer scientist (hardware division) was included. One of these was the ability to increase performance by plugging in more processors. So (I am told), the iAPX432, as this indigestive nightmare came to be called, included a split-transaction bus, but no cache coherency; the iAPX432 didn't have any data caches. It was introduced with great fanfare in late 1980 and quietly died shortly thereafter.
You hardly ever hear of the 432 any more and there are numerous very good reasons for that. Still, Intel learned how to build a split-transaction bus.
The German company Siemens decided that the 432's fault tolerance was a terrific idea. It poured a great deal of money -- some say three-quarters of a billion dollars -- into the BiiN cooperative for development of Intel's 960 series, a.k.a. "Son of iAPX432." Intel introduced the i960MX shortly after Siemens ran out of money in late 1989. It included both a split-transaction bus and logic to maintain cache coherency in multiprocessor systems. Hello, Futurebus!
1992: The P6 Stirs
I'm guessing that 1992 is when Intel got serious about the Pentium Pro (then P6). It was decided that the P6 would be a CPU with not only high performance in its own right, but would include cache-coherency logic built-in to simplify the task of building a 2- or 4-CPU SMP system. The P6 needed Futurebus. Once this decision was made, a lightning-fast "design-in" eventuated: The engineer who designed the i960MX bus (probably using Deutschemarks) was coopted and that bus was incorporated directly into the P6. Voilà!
So the Pentium Pro, shipping for well over a year now, includes the functional equivalent of Futurebus. Much of Volume 1 of the Pentium Pro user manual details just how that split-transaction bus operates. Many industry observers believe that Intel has legally protected the P6's bus, most likely with a pending patent or five. Mirabile dictu, a real-world application for such SMPs has recently emerged -- the network server. Else all that wonderful technology would be used as frequently as Futurebus.
If the P6 is to be used at all, it must be used with the split-transaction bus. The chip does not include an optional simplified bus protocol (or bus signals). But if the P6's bus is, as suspected, legally protected, then Intel's competitors cannot produce a CPU which plugs into a motherboard using a chipset designed for the P6 bus.
Naturally, all of the above considerations apply to the Pentium II (nee Klamath). The same bus is used so that Pentium II can use Pentium Pro chipsets.
Pentium Pro Design Decisions
The Pentium Pro was designed at a time when the makers of fast static RAM (SRAM) for Pentium L2 caches were making a fortune (go back and look at IDT and Cypress' profits for that period!). I've always felt the Pentium Pro design was influenced by a desire on Intel's part to move those profits in-house, in addition to the obvious performance considerations. But then L2 cache SRAM production peaked and the parts moved to commodity status.
I also think that Intel overestimated how fast the mass market would move away from 16-bit code. Perhaps it believed early propaganda that Windows 95 would be a 32-bit operating system. So 16-bit performance was ignored in Pentium Pro's design -- and Intel became the 87,642nd organization to erroneously conclude that the future of high-performance computing in the mass market would be based on symmetrical multiprocessing (SMP).
Intel has just demonstrated to us one of the reasons it remains so successful. It has cut the Pentium Pro loose to find its own (highly limited) way in the SMP web server niche. And it has taken the otherwise excellent Pentium Pro core and fixed those three problem areas to come up with its next hit product -- the Pentium II.
- Intel has tossed out the proprietary cache chip and replaced it with commodity SRAM, with merely a proprietary tag SRAM chip (the Intel 82459).
- Intel has restored logic that will make the Pentium II run 16-bit code swiftly (logic that was once in the original Pentium but was dropped in the Pentium Pro since 16-bit capability was "unneeded").
- And Intel has either removed or will ignore SMP capability in the Pentium II. Oh, yes: MMX has been added to the Pentium II. The result is a great mass-market high-performer that will do to the Pentium market what the Pentium did to the 486 market. (And in the same way. The crossover will take time.)
The Pentium Pro is in that white boat over there, the one sailing into the sunset.
Daughterboard or Substrate?
This brings us to the more obvious feature of the Pentium II -- its unusual physical configuration. Which is not unusual at all.
Let's return to the middle 1980s, when the RISC hype had reached its first peak but the warts were not yet plainly visible. There was a heated race to be first to market with a 32-bit commercial RISC processor. Who won? Some would say that Fairchild's C100 Clipper processor, introduced in 1986, won that race.
The C100 processor used 2-micron design rules. Its 836K transistors were partitioned onto three chips. (All the "single-chip" microprocessors of the day were partitioned into two or more chips!) And at 33 MHz, it was by far the fastest commercial microprocessor of its day.
Just about the time the Clipper was introduced, National Semiconductor bought Fairchild even though Nat Semi already had a wonderful microprocessor, the 32000 series. Intergraph had already designed its product line around the Clipper and bought the rights to the processor from Nat Semi. (A scenario similar to the more recent Silicon Graphics takeover of MIPS.) This muddied the waters....
I have beside me page 77 of May 1989 Electronics magazine, with a chart showing 1988's eight leading vendors of 32-bit RISC chips (source: Dataquest). Intergraph led with shipments of 21,555 units. Motorola's 88100 was second with a mere 2000 units, and Cypress third with the SPARC integer unit, the CY7C601, at 1500.
In other words, the Clipper outsold the second-place RISC processor in 1988 by more than ten to one. In certain quarters this was an untenable situation, not to be endured. The high priests of RISCdom sadly but righteously proclaimed that the Clipper was not a true RISC processor; it was instead to be counted amongst the impure and doomed CISC faction.
(The Clipper has indeed vanished into the mists of history, although it took a while. Likewise, the second place 88100. The fourth-place chip, the AMD 29000, never even made it to the desktop starting block. And MIPS, as a stand-alone commercial enterprise, failed.)
The reason I'm writing about the Clipper now is how it was packaged. It was sold as three major chips plus a clock chip, all mounted on a small circuit card that used a ceramic substrate. Fairchild wouldn't sell the chips separately. Why? That blazing-hot 33 MHz bus speed, that's why. (Don't laugh. In 1986 that was extremely fast.)
Fairchild decided it simply could not trust motherboard designers to produce a reliable layout at that clock rate. So it decided to do the job once -- correctly, for once. Since it was a small board, the use of a ceramic substrate didn't significantly impact the cost. Ceramic helps spread heat and has electrical benefits such as impedance control.
Clipper 1986 -> Pentium II 1997
How does the Clipper relate to the Pentium II? It's the same product (a multichip high-performance processor) packaged in the same way (on a substrate) for the same reason (the very fast signals to/from the cache chips). The two extra Clipper chips were for the cache.
Since Intel had to come up with a new package it undoubtedly decided to patent aspects of its new package. Unprecedented? Take a look at one of those SIMMs in your system. A really simple package, right? Every SIMM you buy generates royalties for Wang Laboratories, which patented that package!
Intel's Foul, Base Motives?
As you can see, the decisions which eventuated in the proprietary Socket 8 and Slot 1 are the logical results of performance-related industry trends. If Intel had no intention whatever of creating proprietary products, the Pentium Pro and Pentium II would be unchanged.
I guess the complainers expect Intel to spend its hundreds of millions of R&D dollars and then give the result away. I've often wondered if these folk are equally generous with their own possessions?
These critics should be careful what they wish for. They could be stuck with a choice of running UNIX on a $14,995 RISC workstation or oozing emulated System 7 on a $7995 Apple PowerMac.
DDJ
