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Power.org and the Power Architecture

With us today is Ray Bryant, chairman of Power.org, an organization that develops and supports Power Architecture technology as an open standard hardware development platform.

DDJ: Ray, can you briefly describe the Power Architecture and tell us what's unique about it?

RB: Certainly. POWER, which stands for "Performance Optimization With Enhanced RISC," comes from the IBM's long history of commercial computing experience and innovation, optimized and enhanced through a collaboration with Apple and Motorola. To this trilogy, IBM brought its background in enterprise computing, Apple brought its perspective on personal computing, and Motorola in networking and communications. More recently, Freescale and Sony have been the closest collaborators, with architecture refinements tailored for gaming and automotive applications. Today, this collaborative model for refining the architecture is formally embodied in Power.org, where customers, ecosystem partners, and chip developers can collaborate on the future of the architecture. In fact, this is another characteristic which differentiates the Power ISA from all others. These partnerships, the open collaborative model of Power.org, and IBM's focus on scalability, reliability, and longevity have shaped the Power Architecture into the unique creation it is today.

It is the inherent scalability of the Power Architecture which we try to capture in our marketing banter; "Set-tops to Teraflops", highlighting a range of applications from satellite digital set-top boxes to super computers. This range is by far, the broadest performance range and market applicability of any processor architecture in history.

The proven reliability of Power Architecture implementations is evidenced by many mission critical applications in aerospace and defense, such as all three Mars Rover landings that used Power Architecture chips. Power Architecture has the leading share of safety-critical Automotive embedded systems and a proven track record of reliability in servers, with the lowest soft error rates under a barrage of proton and neutron radiation.

The architecture underlies an extraordinary range of products, from supercomputers with 213,000 processors to tiny automotive controllers dissipating less than a watt. Power Architecture technology is in everyday household electronics -- printers, HDTVs, video recorders, game consoles -- as well as more exotic electronics, such as satellites and the Mars Landers. The adaptability of our technology platform makes it well-suited for any advanced electronic application and our progressive approach to allow for custom designs based on the architecture makes it the most versatile architecture.

Many different types of solutions and devices are built on the Power ISA. They're marketed by various companies under different product brands. There's PowerPC and PowerQUICC in networking and communications. There's POWER5 and POWER6 in servers. Xilinx uses Power Architecture cores in some of its Virtex FPGAs and Sony, Microsoft, and Nintendo all use Power Architecture to create their game console platforms.

Some more notable characteristics of Power Architecture include:

  • Power Architecture is a 64-bit architecture with a proper 32-bit subset. All code which is written for the 32-bit subset will run on a 64-bit engine, which is unique in the industry. Also, chip developers can create a Power ISA compliant engine with just the 32-bit subset, no floating point processor, minimal register configurations and neither of the optional VMX or SPE accelerator instruction sets, saving critical silicon on embedded applications. Competitors to Power Architecture have either created a completely new 64-bit architecture, which no 32-bit subset, or added 64-bit support as an afterthought, with serious scalability issues resulting.
  • Efficient data moving machine. The Power Architecture is a RISC (Reduced Instruction Set Computer) architecture, not unlike other RISC architectures. All RISC architectures share the common theme of implementing fewer instructions to accomplish a fixed element of work than a CISC (Complex Instruction Set Computer) or VLIW (Variable Length Instruction Word) architecture. The Power Architecture takes this one step further by requiring a relatively large, even in their minimal configurations, set of on-chip registers. These registers serve as short term storage for intermediate results, eliminating the need to write and then read intermediate results using off-engine memory. In addition, the Power ISA has a number of instructions whose sole purpose is to perform complex data movement activities as efficiently as possible, again, avoiding the need to use off-chip memory.
  • Power usage at a system level is dominated by two elements:

    • how many instructions are required to accomplish a fixed element of work
    • how many data reads and writes are required to execute a specific code sequence.

    RISC architecture helps reduce power consumption because of its simplicity, making it an inherently "green architecture". In addition to the choice of full 32-bit or 64-bit data and computation paths, the Power Architecture ISA is also configurable to large market sub-segments, with optional elements at both the Book 1 and Book 3 levels. The base architecture for the entire ISA is implemented in Book 1, where both the VMX and SPE optional extensions are also located. This enables developers to create whole libraries of software for specific target market families such as networking and communications, streaming media, or games. Similarly, Book 3 enables developers to choose a memory subsystem (Server or Embedded) which is most appropriate for their target market.

DDJ: The Power architecture was an early participant in the world of multi-core. How has it kept up with all the current excitement concerning multi-core and concurrency?

RB: To a large extent, multi-core, concurrency, and multi-threading are somewhat separate topics from the underlying architecture. However, IBM Systems and Technology Group and Power Architecture Embedded partners and customers have been implementing multi-core designs for many years. If you think back, the ubiquitous PowerQUICC processors from Freescale, which were launched in the mid '90s, have always been heterogeneous multi-core devices. In 2001, IBM's POWER4 become the first microprocessor to incorporate dual cores on a single die. It also was the first to implement a multi-chip-module containing four POWER4 microprocessors in a single package

For the past 10 years, many of those multi-core designs have supported concurrency via a MESI (Modified, Exclusive, Shared, Invalid) symmetric multi-processing protocol which enables memory concurrency. For the past 8 years, multi-threading has started to also become popular on internal IBM designs, and we expect it will soon eclipse even multi-core in its popularity with industry analysts and editors.

Therefore, we benefit from more than a decade of experience with multi-core implementations and now we have shifted our full focus to the challenge of how to efficiently program and automate software development for multi-core devices. Power.org is addressing this challenge via multiple technical initiatives including adding virtualization support for embedded hyper-visor and other virtualization technologies directly into the Power ISA. This simplifies software development by creating an abstraction layer of capabilities for the underlying cores. ISA support for embedded hyper-visor support will be formally announced in early 2009.

We are also very much focused on balanced system designs using multi-core technology. One advantage for Power Architecture is that it uses a highly scalable memory model. The memory model enables high-performance memory operations with relaxed ordering rules. These relaxed rules enable multi-threaded ordering requirements to be enforced only when required by software, providing much greater throughput in hardware, as operations can be processed as quickly as possible. Most of the coherence and bandwidth optimizations used in POWER-based Enterprise Servers would not be possible with less advanced memory models.

DDJ: From what I've read, the Power architecture has been implemented on platforms from game consoles to supercomputers. What makes this flexibility possible?

RB: This flexibility comes from our unique advantage of being the world's most scalable processor architecture as well as being the most open and collaborative architecture that allows for customization. We also benefit from "raw" technology advantages, enabling relatively small die sizes. This makes our architecture ideal for System-on-Chip (SoC) designs. Finally, Power Architecture and its various routes-to-market enable OEMs to choose high performance, balanced power and performance, or low power.

Almost every Power Architecture processor implementation in the marketplace has been tailored for a specific class of product. For example, AMCC offers its 440 and 460 processors with specialized functions for high-performance storage applications. Freescale has its MPC5-series of microcontrollers, which are ubiquitous in the automotive market. There are also highly differentiated and customized variations of Power Architecture processors in the Nintendo Wii, the X-Box 360 and the Playstation 3. In each of these cases, it's not just a simple matter of loading silicon with application-specific circuits, it's more about making conscious design decisions at the silicon level that enhance the performance of the entire system. The companies behind the Power Architecture platform are experts at making these trade-offs, and they've combined their systems orientation with our fundamental technology advantages to make the architecture extremely adaptable.

DDJ: What kind of software development tools are available for the Power platform?

RBPower is one of the most widely and avidly supported processor architectures in the industry. As would be expected, these tools naturally congregate around the market segments where Power Architecture is popular: Servers, Storage, Networking, Communications, Automotive and Digital Media. Other than Windows, Power Architecture is supported by all major operating system platforms, and most of the minor ones. Compilers (single core, multi-core and multi-threading) are available from IBM (XL C/C++ and XL Fortran), the Linux GNU tree, Wind River, and Greenhills Software. Software development partners (both Server and Embedded) have rallied around the Eclipse framework for nearly a decade now, creating a software development environment that's second to none in the world.

Game consoles, by their nature and business models, are tightly controlled platforms. The programming environment and software development tools for Microsoft Xbox are so tightly controlled it's almost a closed platform. Nintendo's Wii and the Cell game consoles from Sony are popular (and inexpensive) Linux software development platforms, in addition to being proprietary game platforms. For more on Cell development tools, see www.power.org/resources/devcorner/cellcorner and cell.scei.co.jp/e_download.html.

The port of Linux to Power remains the best of breed Linux offering. For information on Linux development on Power, penguinppc.org and ozlabs.org/mailman/listinfo/linuxppc-dev.

In summary, Power Architecture has a wealth of development tools and software in practically any category you can imagine. Many of these tools, operating systems, compilers, etc., have been market-proven and continually enhanced for more than a decade. These are tools and software offerings from companies like Cadence, Wind River, Green Hills, Synopsys, Mentor, LynuxWorks, and the list goes on and on.

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