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The Essentials of the Intel QuickPath Interconnect Electrical Architecture

Dave Coleman and Michael Mirmak are the authors of Mastering High Performance Multiprocessor Signalling, on which this article is based. Copyright (c) 2009 Intel Corporation. All rights reserved.

Intel QuickPath architecture (Intel QPI) is designed to provide efficient scalability both logically and electrically. Intel QPI architecture is a link-based architecture that provides robust point-to-point signaling.

Historical Context and Motivation

System architecture based on the Front Side Bus (FSB) is a well-established design approach for multiple processor systems. As processor and memory architecture have improved and system speed has increased, the FSB has followed suit to maintain a balanced and performing system. This process has continued to succeed for five generations of Intel processors, starting with the Pentium Pro and running through the Pentium 4 processor families.

This shared-bus architecture, continuing the approach of increasing the bus data rates, has reached intrinsic bus challenges for multiple processor systems. Initially configured with five bus loads, 800 million transfers per second (MT/s) was found to be the limiting data rate. Reducing to three bus loads, and then to two, data rates have been pushed to 1333 MT/s. To continue to achieve greater performance, additional FSB interfaces have been added at a cost of 175 signals each, thus requiring memory controllers to become very large devices with more than 1500 pins.

The FSB is designed to provide communication between multiple processors and a single memory controller. Advantages are deterministic in-sequence events, simpler debugging, and observability. However, the FSB brought with it a performance penalty with each added component to the shared bus. With multiple memory controllers in a system, this bus architecture no longer performs adequately. Memory accesses by multiple components in this configuration are already delayed, and with addition of multiple memory controllers, the FSB becomes over-burdened. To compound this, the FSB shares upstream and downstream signaling on individual signals, but supports only unidirectional signaling, not allowing communication simultaneously in both directions. So the FSB either is sending data upstream or downstream on the shared signal wires. Also, the FSB, with 175 signals, is a heavy burden to component pin counts. Lastly, the Gunning Transistor Logic Plus (GTL+) signaling technology is limited to 1.6 gigatransfers per second (GT/s), which limits the interface bandwidth to 12.8 gigabytes per second (GB/s).

The paradigm needs to change in signaling and logical architecture to get to the next level of driving gigabytes per second between components in the printed circuit board (PCB) and improve memory organization and access latencies. Figures 1 through 3 show comparisons of example shared bus systems which use the FSB, a Memory Controller Hub (MCH) and an I/O Controller Hub (ICH). Figures 4 through 6 show examples of systems using various Intel QPI signaling configurations that use point-to-point links with distributed memory controllers and I/O Hubs (IOH). These sets of figures show how the shared bus and Intel QPI architectures are in different performance classes.

Figure 1: Four-Processor Computer System Based on a Single Front Side Bus

Figure 1 shows a system with four processors employing a single shared address and data bus to one chipset component.

  • Key Advantages

    • Simpler bus design, analysis, and debug
    • Global observability among components
    • Deterministic in-sequence events

  • Key disadvantages
    • Limited bus bandwidth, which goes down with additional components added to the FSB.

Figure 2 shows a system with four processors employing two shared address and data busses with point-to-point links to one shared chipset component.

Figure 2: Four-Processor System with Two Front Side System Busses

Figure 3 shows a system with four processors employing four independent address and data busses with point-to-point links to one shared chipset component.

Figure 3: Four-Processor System with Four Independent System Busses

  • Key Advantages

    • Higher bus bandwidth due to point-to-point links

  • Key disadvantages
    • Loss of global observability
    • Couples system debug with out-of-sequence events
    • Chipsets become the bottleneck for memory bandwidth

Figure 4 shows a system with two processors employing Intel QPI links to one chipset component.

Figure 4: System with Two Processors Employing Intel QuickPath Interconnect Technology

Figure 5 shows a system with four processors employing Intel QPI inks to two chipset components.

Figure 5: System with Four Processors Employing Intel QuickPath Interconnect Technology

Figure 6 shows a system with eight processors employing Intel QPI links to four chipset components.

Figure 6: System with Eight Processors Employing Intel QuickPath Interconnect Technology

These figures show some possible configurations of two-, four-, and eight-processor systems respectively that can be built using the Intel QPI (indicated by the red arrow pairs in the figures). Each processor typically has a memory controller on the same die, allowing systems to be more scalable in performance. However this is not essential and systems can have separate, discrete memory controllers. Similarly, the I/O subsystems can either be incorporated onto the same die as the processors or built as separate I/O hubs.

These systems have multiple Intel QPI links connecting the devices to each other. Each one of the links can operate independently of the other links. The performance of such systems can be very high, particularly if the processors are allocated independent tasks, working on data that are optimally distributed across the different memory controllers and close to their own processors. Most current operating systems do recognize such system configurations with Non-Uniform Memory Accesses (NUMA) from each processor and the OS places the data in the memory accordingly.

  • Key Advantages

    • Higher bus bandwidth due to point-to-point links
    • Efficient memory organization and lower memory access latencies
  • Key disadvantages

    • Loss of global observability
    • Couples system debug with out-of-sequence events

In Figure 6 the memory arrays have been left out and the Intel QPI links are depicted as single lines for clarity. The systems shown in Figures 4 through 6 are fully connected, at least in that each processor has a direct link to every other processor in the system.

The point-to-point links use fewer signals than the shared bus architecture and provides higher bandwidth, transferring data in both directions simultaneously. The interface also supports multiple memory controllers and efficiently manages the coherence of the processor caches in the system, which is needed for a multiple processor and scalable server systems. The interface provides a robust set of mechanisms to handle errors and recover from them without shutting down the entire system. Intel QPI is defined to meet these needs.

Serial signaling architectures, such as PCI Express, USB, and SATA take advantage of "packet-based" differential signaling to provide higher signal fidelity and protocol flexibility, and some data reliability as well. Intel QPI architecture is constructed to include these capabilities, as well as additional logical and electrical features, to take advantage of both parallel and serial architectures described later in this article.

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