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April 15, 2014

Inside an Automated State Machine

I was pleased to see that the generated code was reasonably easy to understand

April 07, 2014

State of Automation

The truth is, I have mixed feelings about automated tools for code generation

April 01, 2014

Easy Verilog Test Benches

I wouldn't dare try to code up a massive test bench like the ones I use for my CPU designs using this method