Zhejiang University
Intel-ZJU Embedded Technology Center, College of Computer Science And Technology
[email protected], [email protected], {zjsqs,hjw}@zju.edu.cn
Scalability of the core frequency is a common feature of low-power processor architectures. Many methods for frequency scaling have been proposed to find the best trade-off between energy efficiency and computational performance. Embedded hardware monitors in the form of event counters have proven to offer valuable information in the field of performance analysis. We can get some clues from that, this will be helpful for us to find the target frequency.
In this paper, we introduce a new algorithm to obtain the target frequency which benefit from the performance monitor counters. And once the system information changes, which means we can change the core frequency to perform at a lower power consumption, the core frequency will be changed through our method in the next time slice.
Experimental results, based on measurements on the platform with Intel pxa255 processor, show that significant energy savings are achieved with little performance degradation. With some good situations the energy savings can go up to about 10 percent (with little performance loss). The proposed algorithm is effective in the power-aware and real-time systems.
This paper was originally presented at the Eighth Real-Time Linux Workshop held at the at the School for Information Science and Engineering, Lanzhou University, in Lanzhou, China.
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