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Debugging Makefiles


Why Did File foo Get Built?

Here's an example Makefile that builds two object files (foo.o and bar.o) from corresponding C source files (foo.c and bar.c). The two object files are linked together to create an executable called "runme":


 .PHONY: all
 all: runme
 runme: foo.o bar.o
   @$(LINK.o) $^ -o $@
 foo.o: foo.c
 bar.o: bar.c
 %.o: %.c
   @$(COMPILE.C) -o $@ $<

Now suppose that runme, foo.o, and bar.o are all up to date. Altering foo.c clearly rebuilds foo.o and relinks runme. In this example, you can follow the chain of dependencies and see that runme being relinked could have been caused by a change to foo.c. In a larger Makefile, following dependencies is next to impossible.

If you used GNU Make's -d option to follow the chain foo.c caused foo.o to build, which caused runme to relink, you'd be faced with walking through 556 lines of debugging information. Imagine trying the same thing on a real Makefile. However, a small change to the Makefile causes GNU Make to reveal exactly the chain of events. Inserting the following in the Makefile causes GNU Make to output information about each rule that's being executed, and why it was executed:


OLD_SHELL := $(SHELL)
SHELL = $(warning [$@ ($^) 
            ($?)])$(OLD_SHELL)

Here's the output when foo.c had just been modified but everything else was up to date:

Makefile:11: 
    [foo.o (foo.c) (foo.c)] 
Makefile:5: [runme (foo.o bar.o) 
    (foo.o)]

There's a lot of information in those lines. Each line has the name of the Makefile and the line number of the rule that's executing (line 11 is the pattern rule %.o: %.c used to build foo.o from foo.c, and line 5 is the rule to link runme). Within the square brackets there are three pieces of information: the target that's being built (first the Makefile is building foo.o and then it's building runme); then the full list of prerequisites of that target (so foo.o is built from foo.c, and runme is built from both foo.o and bar.o); finally, there are the names of any prerequisites that are newer than the target (foo.c is newer than foo.o, and foo.o is newer than runme).

The second piece of information in parentheses gives the reason a target was being built: It's the list of newer prerequisites that force a rebuild. If the parentheses are empty, it indicates that there are no newer prerequisites and that the target is being rebuilt because it does not exist.

How this works is what I call the "SHELL hack." GNU Make stores the path of the shell it uses to execute commands in the SHELL variable. It's possible to modify SHELL to set your own shell. If you do, GNU Make checks the value of SHELL every time it is about to execute a rule. That checking per rule gives us the opportunity to do something on a per-rule basis. In the aforementioned code the actual shell is stored in OLD_SHELL by grabbing the value of $(SHELL) using an immediate assignment (:=). Then the SHELL is modified by preprending it with a call to $(warning...). The $(warning...) uses three GNU Make automatic variables to print the name of the target being built ($@), the complete list of prerequisites ($^), and the list of prerequisites that are newer than the target ($?).

Since GNU Make expands SHELL every time it wants to run a rule, and it does this after setting the automatic variables for the rule, the $(warning...) gets expanded giving the output shown earlier. This SHELL hack is powerful and can be used to great effect in relating GNU Make log file output to Makefiles.


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