USB Initialization: The USB controller supports both Enhanced Host Controller Interface (EHCI) and Extensible Host Controller Interface (xHCI) hardware. Enabling the host controller for standard PCI resources is relatively easy. It is possible to delay USB support until the OS drivers take over. If pre-OS support for EHCI or xHCI is required, then the tasks associated with the USB subsystem become substantially more complex. Legacy USB requires an SMI handler be used to trap port 60 and 64 accesses to I/O space, converting these to the proper keyboard or mouse commands. This pre-OS USB support is required if booting to USB is preferred.
SATA Initialization: A SATA controller supports the ATA/IDE programming interface as well as the Advanced Host Controller Interface (AHCI). In the following discussion, the term "ATA-IDE Mode" refers to the ATA/IDE programming interface that uses standard task file I/O registers or PCI IDE Bus Master I/O block registers. The term "AHCI Mode" refers to the AHCI programming interface that uses memory-mapped register and buffer space and a command-list-based model.
The general guidelines for initializing the SATA controller during POST and S3 resume are described in the following sections. Upon resuming from S3, system BIOS is responsible for restoring all the registers that it initialized during POST.
The system BIOS must program the SATA controller mode prior to beginning other initialization steps. The SATA controller mode is set by programming the SATA Mode Select (SMS) field of the port mapping register (
D31:F2:Reg 90h[7:6]). The system BIOS may never change the SATA controller mode during run-time. Please note that the availability of the following modes is dependent on which PCH is in use. If system BIOS is enabling AHCI Mode or RAID Mode, system BIOS must disable
D31:F5 by setting the SAD2 bit,
RCBA + 3418h. The BIOS must ensure that it has not enabled memory space, I/O space, or interrupts for this device prior to disabling the device.
IDE mode is selected by programming the SMS field,
D31:F2:Reg 90h[7:6] to
00. In this mode, the SATA controller is set up to use the ATA/IDE programming interface. The 6/4 SATA ports are controlled by two SATA functions. One function routes up to four SATA ports,
D31:F2, and the other routes up to two SATA ports,
D31:F5. In IDE mode, the Sub Class Code,
D31:F2:Reg 0Ah and
D31:F5:Reg 0Ah are set to
01h. This mode may also be referred to as "compatibility mode," as it does not have any special OS driver requirements.
AHCI mode is selected by programming the SMS field,
D31:F2:Reg 90h[7:6], to
01h. In this mode, the SATA controller is set up to use the AHCI programming interface. The six SATA ports are controlled by a single SATA function,
D31:F2. In AHCI mode the Sub Class Code,
D31:F2:Reg 0Ah, is set to
06h. This mode does require specific OS driver support.
RAID mode is selected by programming the SMS field,
D31:F2:Reg 90h[7:6] to
10b. In this mode, the SATA controller is set up to use the AHCI programming interface. The 6/4 SATA ports are controlled by a single SATA function,
D31:F2. In RAID mode, the Sub Class Code,
D31:F2:Reg 0Ah, is set to
04h. This mode does require specific OS driver support.
To allow the RAID option ROM to access all 6/4 SATA ports, the RAID option ROM enables and uses the AHCI programming interface by setting the AE bit,
ABAR + 04h. One consequence is that all register settings applicable to AHCI mode set by the BIOS have to be set in RAID as well. The other consequence is that the BIOS is required to provide AHCI support to ATAPI SATA devices, which the RAID option ROM does not handle.
PCH supports stable image-compatible ID. When the alternative ID enable,
D31:F2:Reg 9Ch  is not set, the PCH SATA controller will report the Device ID as
It has been observed that some SATA drives will not start spin-up until the SATA port is enabled by the controller. In order to reduce drive detection time, and hence the total boot time, system BIOS should enable the SATA port early during POST (for example, immediately after memory initialization) by setting the Port x Enable (PxE) bits of the Port Control and Status register,
D31:F2:Reg 92h and
D31:F5:Reg 92h, to initiate spin-up.
Defining the Memory Map
In addition to defining the caching behavior of different regions of memory for consumption by the OS, it is also firmware's responsibility to provide a "map" of system memory to the OS so that it knows what regions are available for use.
The most widely used mechanism for a boot loader or an OS to determine the system memory map is to use real mode interrupt service
20h (INT15/E820), which must be implemented in firmware.
Region Types: There are several general types of memory regions that are described by this interface:
- Memory (1): General DRAM available for OS consumption.
- Reserved (2): DRAM addresses not for OS consumption.
- ACPI Reclaim (3): Memory that contains ACPI tables to which firmware does not require run-time access.
- ACPI NVS (4): Memory that contains all ACPI tables to which firmware requires run-time access. See the applicable ACPI specification for details.
- ROM (5): Memory that decodes to nonvolatile storage (for example, flash).
- IOAPIC (6): Memory that is decoded by IOAPICs in the system (must also be uncached).
- LAPIC (7): Memory that is decoded by local APICs in the system (must also be uncached).
Region Locations: The following regions are typically reserved in a system memory map:
- 00000000-0009FFFF: Memory
- 000A0000-000FFFFF: Reserved
- 00100000-xxxxxxxx: Memory (The xxxxxxxx indicates that the top of memory changes based on "reserved" items listed below and any other design-based reserved regions.)
- TSEG: Reserved
- Graphics Stolen Memory: Reserved
- FEC00000-FEC01000*: IOAPIC
- FEE00000-FEE01000*: LAPIC
Loading the Operating System
Following configuration of the memory map, a boot device is selected from a prioritized list of potential bootable partitions. The "Load Image" command, or
Int 19h, is used to call the OS loader, which in turns load the OS. And off we go.
This article is adapted from material in Intel Technology Journal (March 2011) "UEFI Today: Bootstrapping the Continuum," and portions of it are copyright Intel Corp.
Pete Dice is a software architect in Intel's chip-set architecture group.