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Parallel Updates Instruction Set has announced the release of Power Instruction Set Architecture (ISA) Version 2.06, which incorporates significant advances for server and embedded applications that improve performance and efficiency, and speed design cycles

Power ISA Version 2.06 defines significant extensions for the embedded environment including an enhanced memory management architecture, logical partitioning and hypervisor support, embedded page table support, and multi-threading. It contains a new vector-scalar floating-point facility that merges and extends existing vector and scalar floating-point operations; numerous new fixed-point, floating-point, and memory-management instructions; a new storage attribute in support of strong storage access ordering; new storage control features, and many other enhancements.

For server applications, Power ISA Version 2.06 includes major extensions to the scalar and SIMD (Single Instruction Multiple Data) floating-point architecture. The Vector-Scalar Extension (VSX) unifies and extends the existing scalar floating-point and vector facilities to improve floating-point performance for compute-intensive tasks. VSX introduces support for double-precision floating-point vector operations and consolidates the existing vector and floating-point scalar registers into a unified 64-entry register file. These enhancements enable increased parallelism in double-precision floating-point processing with better execution pipeline utilization, leading to increased application performance.

For embedded designers, Power ISA Version 2.06 offers some significant enhancements:

  • Support for virtualization and hypervisors including a new guest mode and Memory Management Unit (MMU) extensions that enable the efficient implementation of hypervisors on the embedded Power Architecture platform. It allows a more efficient implementation of virtualization overall, partitioning of embedded systems, the isolation of applications and resource sharing, well-known techniques that previously were available only for the server market.
  • The high-level memory management framework of previous architecture versions has been replaced by a detailed architecture based on the Freescale MMU model and extended to support virtualization and enhanced performance. This provides a single programming model to streamline future software development that formerly needed to cope with a variety of MMUs from multiple companies.

Page Table support has been added to the embedded architecture specifically to enhance the performance of the LINUX operating system running on embedded Power Architecture platforms. This provides a more natural way to perform address translation and can significantly speed up applications, where translation is a bottleneck.

Multi-threading for the embedded environment, while well-known on the server platform, Power ISA Version 2.06 includes explicit support for the execution of multiple threads on an embedded core. Multi-threading enables significant improvements in application throughput on the embedded platform.

"Power Architecture technology is a modern platform that continues to adapt to new market-driven requirements and break new ground in areas like virtualization and performance," said Wolfram Sauer, chairman of the Power Architecture Advisory Council and manager of systems architecture at IBM. "Offering a host of refinements and additions, this newest version of the ISA has the potential to make a tremendous performance difference in both server and embedded applications."

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