SEAForth 40C18 Architecture
SEA is for Scalable Embedded Array multicore processors and Forth is for Forth because you program these in a tiny Forth that fits the memory model of array processing.
It's called the 40C18 because it's forty C18 cores (an earlier Chuck Moore architecture was the C16) running asynchronously in a 4x10 matrix with N-S-E-W interprocessor communication automatically synchronized.Each core is an 18-bit dual-stack Forth machine with 32 opcodes, 64 words of local RAM, 64 words of local ROM, 18-bit registers and a 10-bit address bus.
Certain edge nodes can do various types of external I/O, which is how the chip can talk to the outside work beyond the data and address buses. No node internal to the matrix can do external I/O, hence programs are whispered down the lane from node to node. The interprocessor read address can be the program word fetch.
The stacks are 8 entries circular with a TOS and S (second-on-stack) regiser for the Data stack (making 10 total data stack positions) and R for the Return stack (making 9 total return stack positions). Circular means if you keep pushing you overwrite. As the 40C18 data sheet sublimely reads,
The concept of stacks being full or empty represents an assumption in software ... There is no hardware detection of stack overflow or underflow conditions.
A node can pass a program load to an adjacent (up, down, right, left) node including an load address and address which the receiving node should start execution. At any time, if the nodes agree to do so, a given node A can pass an instruction word to an adjacent node B which jumps to the port address for an instruction fetch. When A writes such a word, A sleeps until B reads and accepts; if B goes to read, B sleeps until A writes such a word.
Some previous posts about the SEAForth chips: