Jack is a senior project manager at Vesta Technology Inc., in Wheat Ridge, Colo. Jack can be reached as [email protected], as JAX on GEnie, or as the Sysop of the RCFB BBS, 303-278-0364.
Writable Instruction Set Computers, or "WISC" for short, are devices that blend the best of CISC and RISC into a single simple architecture. Because of their simplicity, WISC devices allow the programmer to tinker with the internals of the instruction set. In this article, I examine WISC Technologies' (Box 429, La Honda, CA 94020) CPU/16 processor and put it through some of its paces by writing the microcode for an oddball instruction or two.
Dual-Stack WISC
The CPU/16 is a dual-stack word-addressing central processing unit designed in discrete logic. At power up, the entire CPU/16 microcode store is both empty and writable. The CPU/16 is dependent on the host computer (nominally a PC or AT, though other interfaces could be devised) for the powerup load of its microcode and program. The microcode and program that come with the CPU/16 implement MVP-Forth/16 and contain a number of benchmark examples that illustrate the speed attainable by application-specific instruction sets. Even with the entire Forth system and special benchmark instructions, about half the CPU/16 microcode store is unused and thus available to the ambitious microcode composer.
The microassembler, microcode, and cross-assembler that come with the CPU/16 are provided both compiled and in MVP-Forth source code form. The WISC programmer is thus confronted with the paradox of one of the purest Forth programs ever written, coupled to an old-fashioned, file-less BLOCK-only Forth development system. No matter: As indicated, the source is one of the classics of Forth, sparsely commented and eminently comprehensible. It takes about four hours reading to grasp the essentials of WISC development.
The CPU/16 has two stacks, DS and RS, each with its addressable stack pointer, DP and RP. The top item on each stack may be an input to the ALU. In addition, DHI serves as a top-of-data-stack cache and as input B to the ALU, and is paired with DLO for shifts. DLO also serves as a sort of scratch register.
RAM is addressed using the program counter, PC, as a RAM pointer. For this reason, the program counter value is automatically latched at the beginning of every microcode instruction into a register called PCSAVE, so that the program counter may later be restored if it is used as a RAM pointer in the course of execution of an instruction.
Warren Abstract Machine "deref"
Much in the manner that Forth can be expressed as a virtual machine design the silicon embodiment of which has been attempted in projects such as the Novix, Harris RTX, FRISC-32 (SC32), and the CPU/16 itself, Prolog, too, has its virtual machine architecture (known as the "Warren Abstract Machine" after David Warren, one of the original proponents of such a concept).
Using Hassan Ait-Kaci's Warren's Abstract Machine (MIT Press, 1991) as my guide, Listing One (page 89) implements the WAM "deref" procedure as a single instruction, WAM-DEREF.
The Warren Abstract Machine "deref" procedure is described by Mr. Ait-Kaci as that "...which, when applied to a store address, follows a possible reference chain until it reaches either an unbound REF cell or a non-REF cell, the address of which it returns." In other words, the first in a series of Prolog variables, each of which points to the next, may be resolved to a final unbound variable (that is, a variable which points to itself) or to a final nonvariable (an object tagged otherwise than as a variable).
WAM-DEREF assumes that references are stored in the order [tag],[address]. WAM-DEREF first checks that the object whose address is on top of the data stack does not point to itself. If it does, that same address will be returned. If the object points to a different object, WAM-DEREF will get a copy of the current tag and proceed to that distant reference.
If the tag of the new object does not match the previous object's tag, the new object's address is returned and WAM-DEREF exits.
If the tag of the previous object is identical to the tag of the new object, then the new object is examined to see if it points to itself. If so, its address is returned and WAM-DEREF exits. If the new object points to some other object, the program counter is reloaded without increment so that the invocation of the WAM-DEREF instruction repeats, but with the latest address in the top of stack cache.
WAM-DEREF makes no assumption about the tag's nature. I tested this instruction by creating the following structures:
CREATE FOO 0,0, CREATE WOOF 1, FOO, CREATE ZOTZ 1, WOOF,
at which point ZOTZ WAM-DEREF returned the address of FOO. Changing WOOF to point to itself via WOOF DUP 1+! on the word-addressing CPU/16 causes ZOTZ WAM-DEREF to return the address of WOOF, as does changing WOOF's tag to any number other than 1.
Multiple-page Microcode
The WISC microcode store consists of 256 pages of eight 32-bit micro instructions. Through absolute branches (for example, JMP=110) and conditional branches (that is, JMP=00E) are possible within a microcode page and the microcode page counter can be incremented to the next page by a microinstruction, there is no way to decrement the microcode page counter. This is the reason for the trick employed in WAM-DEREF generates a repetitive dereference by reloading the program counter with its previous unincremented value.
Silicon in the Wind
In our dynamic profession, computer concepts appear, disappear, and reappear. An example is the analog computer, which to a large extent disappeared two decades ago. Yet the hardwired neural net, that precocious brat of the '80s, is an analog computer. Who can tell when the time will come for the writeable instruction set computer to have its day in the sun?
_WRITABLE INSTRUCTION SET COMPUTERS_ by Jack J. Woehr[LISTING ONE]
<a name="0030_0009"> \ DEREF a' la Warren Abstract Machine DECIMAL 166 OPCODE: WAM-DEREF ( addr1 -- addr2) 0 :: SOURCE=ALU ALU=B DEST=PC ;; \ RAM pointer := TOS 1 :: INC[PC] ;; \ RAM pointer++ 2 :: SOURCE=RAM ALU=AxnorB ;; \ @RAM pointer == TOS ?? 3 :: SOURCE=RAM ALU=AxnorB ;; \ test takes 2 cycles 4 :: SOURCE=RAM ALU=A DEST=DLO INC[MPC] JMP=11E ;; \ Jump to 6 if not equal, 7 if equal. Note that the microprogram counter is \ incremented in this instruction. The next microinstruction will branch to \the next page. Note also that this microinstruction saved the address pointer \in DLO for later use. 6 :: SOURCE=ALU ALU=B DEST=PC JMP=000 ;; \ Re-load RAM pointer with original address, we are continuing \ via 0 on the next page, since we have run out of space here. 7 :: SOURCE=PCSAVE ALU=A+1 DEST=PC JMP=110 ;; \ Reload Program Counter, we are leaving via 6 on the next page. 167 CURRENT-PAGE ! 0 :: SOURCE=RAM ALU=A DEST=DHI ;; \ DHI := tag 1 :: SOURCE=DLO ALU=A DEST=PC ;; \ RAM pointer := next addr 2 :: SOURCE=RAM ALU=AxnorB ;; \ Compare tags 3 :: SOURCE=RAM ALU=AxnorB ;; \ Comparison takes two cycles 4 :: SOURCE=DLO ALU=A DEST=DHI JMP=11E ;; ( Jump = 6+boolean) \ Jump to 6 is tags were equal, to 7 if different. This microinstruction loads \ DHI (top of stack) with the current address under examination. Therefore, if \ this instruction is re-entered, it will have same entry conditions as \ previously, but starting at the next reference in the chain. \ This is the exit pointed to by both microinstruction 7 on previous microcode \ page, and by the conditional branch in instruction 4 on this page. 6 :: SOURCE=PCSAVE ALU=A+1 DEST=PC INC[MPC] JMP=101 ;; \ Our exit is long and tortuous! We are exiting via 0 on the next page. 5 :: JMP=000 ;; \ This microinstruction is the exit for both 6 and 7. \ This is where "different tags" takes us ... we "fool" the CPU/16 \ into re-executing with original PC value. 7 :: SOURCE=PCSAVE ALU=A DEST=PC INC[MPC] JMP=101 ;; \ We are looping by reloading Program Counter with the same address \ as it contained at entry. But again we are out of room on this \ microcode page, so we must finish on the next microcode page. 168 CURRENT-PAGE ! \ Increment microcode page under compilation. 0 :: DECODE ;; \ Latch new program counter value. 1 :: END ;; \ Exit to next instruction. ;;END
Copyright © 1992, Dr. Dobb's Journal
