The simplest programmable logic is a PLA, or Programmable Logic Array. This is only a little more sophisticated than the memory example. Essentially, you can specify a simple Boolean equation (consisting of the logical OR of the inputs AND'ed in various ways). Instead of just storing the bit pattern, these chips use memory elements to essentially make or break connections. This technology became popular in the late 1970s, when memory was expensive to produce and the simplification made the devices small and affordable. You still see PALs, or their reprogrammable cousin the GAL (Generic Array Logic), used for very simple logic. For example, a single board computer might use a GAL to decode the address bus to select different banks of memory. You can think of a GAL as a PAL that uses some sort of erasable memory element.
The next step up from a GAL is a CPLD (Complex Programmable Logic Device). These devices are like many GALs put in one package with some bits that can connect the GALs together in some way. In addition, the constituent blocks are more than just a simple combinatorial logic block. They typically also contain a 1-bit memory element known as a flip flop. Xilinx, a popular vendor of CPLDs and other programmable logic, calls these elements "macrocells". Altera calls them "logic elements". In practice, you don't care, because you are going to use a high-level method to describe what you want the chip to do.
In general, CPLDs have their own reprogrammable memory. You program them and then they retain their "personality" until you reprogram them. However, they are usually fairly small, though not as small as a typical GAL. For example, one popular Xilinx CPLD has 108 macrocells. That's enough for some reasonably sophisticated logic, but not huge. In particular, anything that consumes a flip flop is going to eat one macrocell, so forget building a CPU with 10 16-bit registers on it! That would take 160 macrocells just for the registers.
The next step up is an FPGA (Field Programmable Gate Array). These devices have a more sophisticated cell structure and a different way of interconnecting the cells. In most cases, the FPGA will have many gates and the memory element that programs the cells will be RAM memory. Practically, that means that every time the chip powers up, something has to load the RAM with the right configuration bitstream. That something might be an EEPROM, a microcontroller that wants to use the FPGA, or a PC connected to the device through a JTAG cable. There are a few FPGA devices that retain their configuration like a CPLD does.
The internal arrangement of the FPGA is different, but practically you will use the very same software to program it so you often don't care so much. However, what you do care about is density. Where a CPLD might have 108 macrocells, an FPGA might have hundreds of thousands of more powerful function blocks. In fact, Xilinx recently shipped an FPGA with 2 million logic cells (which Xilinx claims is enough to implement about 20 million logic gates). For reference, an Intel Pentium has just over 3 million transistors, and a logic gate usually takes more than one transistor. So it is safe to say you could easily reproduce a Pentium inside of 2 million logic cells.
You will probably never run into an ASIC (Application-Specific Integrated Circuit) but it is certainly a programmable logic device. You use the same tools, but instead of memory bits, the tools generate instructions for how to manufacture metal interconnections. The IC factory fabricates this metal interconnect when the chip is made. ASICs are not reprogrammable, and you rarely use them unless you are making a lot of devices. You also have to be absolutely sure your design works, since that first ASIC is very expensive to produce.
Speaking of tools, it is tempting — if you are an old electronics guy like me — to think that you will just draw logic diagrams (schematics) and let the tools do the work to generate a bitstream for your FPGA (or CPLD or whatever).
It is true that the tools can do this. It is also true that many people (including me) are certain that they don't need anything else. It doesn't take long to realize, however, that you do. Here's why. Suppose I ask you to design a CPLD that will take a 4-bit input that ranges from 0 to 9. The output will drive a seven-segment LED display (like this but in hardware).
You could go figure out all the AND, OR, and NOT gates required to do each segment. You'd have to draw a bunch of gates (see page 5, for example). But what if you could write a bunch of formulae instead? For example, segment
a is only on for numbers 0, 2, 3, 5, 7, 8, and 9. It would be easier to write:
assign a=(x==4'h0 || x== 4'h2 || x==4'h3 || x==4'h5 || x==4'h7 || x==4'h8 || x==4'h9)?1'b1:1'b0;
That's a line of Verilog, and if you read C, you can probably figure out what it means with no real explanation necessary. You simply need a line like this for each segment (seven total). There is another popular language known as VHDL that looks more like Ada, but has the same purpose. Either of these is much simpler to manage than drawing a bunch of gates.
Next time, I'll show you how you can use Verilog, starting with combinatorial logic and we'll work up from there.