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Hardware-Assisted Breakpoints


June, 2005: Hardware-Assisted Breakpoints

Register Name Purpose CRn CRm
(a)
TX Register (TX) Communication with JTAG debugger. 8 0
RX Register (RX) Communication with JTAG debugger. 9 0
Debug Control & Status Register (DCSR) Flags for enabling debug mode. 10 0
Trace Buffer Register (TBREG) Reading from trace buffer. 11 0
Checkpoint Register 0 (CHKPTO) Reference address for use with trace buffer. 12 0
Checkpoint Register 1 (CHKPT1) Reference address for use with trace buffer. 13 0
TXRX Control Register (TXRXCTRL) Communication with JTAG debugger. 14 0
(b)
Process ID (PID) Remapping current process addresses to slot 0. 13 0
Instruction breakpoint register 0 (IBCR0) Address of instruction breakpoint 0. 14 8
Instruction breakpoint register 1 (IBCR1) Address of instruction breakpoint 1. 14 9
Data breakpoint register 0 (DBR0) Address of data breakpoint 0. 14 0
Data breakpoint register 1 (DBR1) Address of data breakpoint 1. 14 3
Data Breakpoint Control Register (DBCON) Configures data breakpoints. 14 4

Table 1: XScale debug registers and PID: (a) CP14 registers; (b) CP15 registers.


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