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Software to Hardware Parallelization


The Advanced Encryption Standard (AES) algorithm is another CPU-intensive piece of code. The main pseudocode is:

case 128: ROUNDS = 10; break;
case 192: ROUNDS = 12; break;
case 256: ROUNDS = 14; break;
*/
   KeyAddition(data,round_key[0]);

/* at most ROUNDS-1 ordinary rounds */
  for(r = 1; (r <= ROUNDS) ; r++) {
	Substitution(data);
	ShiftRow(data);
	MixColumn(data);
	KeyAddition(data,round_key[r]);
}
/* do the last, special, round: */
	Substitution(data);
	ShiftRow(data);
   KeyAddition(data, round_key[ROUNDS]);
}
done;


The AES algorithm can be broken down into four subroutines: Substitution, ShiftRow, MixColumn, and KeyAddition. In the aforementioned sample, one block of 16 bytes as a 4×4-byte matrix is run through the entire algorithm. In a pipelined version, when one block of data is encrypted with the first subroutine, it moves to the second subroutine and a new block of data is initiated in the first routine—coarse-grain parallelism at the function level. In addition, each subroutine may run in parallel (fine-grain parallelism). As an example, let's look at the ShiftRow routine.

The ShiftRow routine modifies each row of the state matrix. The top row is not changed; the next row is rotated left one position, the following row two positions, and the bottom row three positions. A processor must modify each row, then go to the next row. In an FPGA, all rows can be changed in one clock.

Today, there are few commercially available tools that automatically do software parallelization, and those that exist are still in their infancy. The next generation of tools will have to address issues such as coarse-grain versus fine-grain parallelism, recursion, and data dependencies and flow, and various performance issues such as load balancing between the host system CPU and the accelerator (bus hogging, memory access bandwidth, data transfer bottlenecks, and the like).


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