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Design

The One Instruction Wonder


Tool Chain

Assuming you have a bunch of Verilog, how do you get it to the hardware? First, most designs will require more than just straight Verilog. You also need constraints which tell the software how to handle certain parts of the Verilog. For example, the parts of One-Der that read the push buttons or drive the LEDs must connect to certain external pins on the FPGA. Without constraints, the translator software will assign them to arbitrary pins which could cause results ranging from things not working, to physically damaging the device by shorting out something on the board.

There are several ways to include constraints. You can put special comments in your Verilog, but I prefer to use a constraint file. The Xilinx tools even include a GUI editor for constraint files to simplify the task.

There are other files you may need. The Xilinx tools have a variety of wizards and code generators that allow you to use GUIs to generate special functions (for example, memory or clock circuits). These files will also be a part of your project.

Xilinx provides several versions of their ISE software which is what you'll use to convert your project into a file that you can download to the FPGA. One version -- WebPack -- is available for free and is all you'll need for many projects. The tool performs several steps to arrive at the final product. First, it does synthesis, mapping your logic descriptions into primitive logic. When this is successful, that logic is mapped to the available FPGA structures. Finally, the structures are arranged on the FPGA and the tool selects how the structures will be interconnected (a process called place and route). Each logic block and interconnect has a certain delay associated with it, so the tool may have to try many different possibilities to arrive at an arrangement that will meet your desired clock speed (the clock speed is specified as a constraint and arriving at a workable solution is known as "meeting timing." For a complex design like One-Der, these steps can take quite some time, even on a fast PC. Once place and route completes, the tools generate a bit file -- an image that you can download to the FPGA using the Xilinx-provided tools (usually using a JTAG cable connected to a printer port or a USB port).

To map these operations to the typical software development flow, you can consider ISE a compiler and linker. The synthesis is roughly analogous to compiling source code to assembly language and the mapping is a little like an assembler converting to binary codes. The place and route step is somewhat like linking everything together, although that analogy doesn't cover everything since a real linker can just put all the output objects in any order. The FPGA router has to use the limited interconnects to get everything that needs to communicate connected.

For smaller designs, you can also use ISE to simulate your work without downloading to the actual IC. In fact, I often do this with small parts of One-Der, but the entire CPU is so complex it is difficult (and slow) to simulate well so I usually try to debug directly on the hardware (although simulating an individual functional unit is relatively easy). Xilinx also provides a tool (but not for free) called ChipScope that allows you to perform basic logic analysis by building a dedicated logic analyzer into the FPGA alongside your design. The analyzer accepts commands and sends data to your PC via the FPGA's JTAG port (the same port you use to program the FPGA during development).

For creating One-Der programs I have a simple cross assembler that uses a combination of awk, and the system's C compiler to output binary in several formats. The mem2flash script (available here) lets you load binary from the assembler directly to the chip's on board flash without having to rebuild the processor just to get a new program loaded.

Road Map

The complete source code for One-Der is available here. Here's a road map to the source code and a summary of what you'll find in each one:

  • topbox.v. This is what connects One-Der to the outside world. I tried to make sure nearly all the board-specific and Spartan 3 specific items show up in this file. The CPU originally used a single clock (the bus would charge on the rising edge and latch on the falling edge) but this made it difficult to do certain memory accesses and limited the CPU speed unnecessarily. After several experiments, I finally decided on using two clock signals, one the inverse of the other and have each instruction take two cycles. The first cycle essentially decodes the instruction while the second one. This file also handles providing a reset signal to the CPU.
  • topbox.ucf. The constraints for topbox make certain the switches and LEDs are all connected to the right pins for the Digilent board. Note that PB3 is the reset switch and not used for I/O.
  • newclock.xaw. Automatically generated from the clocking wizard, this file provides the ganged DCMs used in topbox.
  • oneder.v. This is the main CPU code that implements the bus.
  • program.v. This simple file decodes memory addresses and provides access to bflash or rom depending on the address.
  • rom.v. This automatically generated file represents a small boot ROM (One-Der boots to ROM placed near the top of memory). The change the contents, edit rom.coe and regenerate the rom core.
  • bflash.v. Another automatically generated file. This is the emulated flash where One-Der gets its program code. Note to change the program you need to change the program.coe file and then manually regenerate the bflash core (the Xilinx tools do not detect that the program.coe file changed). However, the mem2flash script can replace the flash contents on the fly without requiring a rebuild of the CPU.
  • FPC.v. The program counter functional unit.
  • FIO.v, Debouncer.v, DisplayHex,v, uart.v, rcvr.v, txmit.v. The I/O functional unit and its components.
  • FMem.v, FMemStack.v, dualmem.v. These modules provide access to memory (provided by dualmem -- an automatically generated dual port memory on the FPGA). Both FMem.v and FMemStack.v share the single memory array. Note that the stack snoops the bus during a subroutine call to save the return address.
  • FAcc.v, cmp.v FByte.v, FLoop.v, Fconstant.v. Other functional units.
  • FReg.v. The register array. Note that register 0 is used to indirectly address other registers. Reading or writing register 0 actually reads or writes the register pointed to by register 1.
  • bflash.bmm. This file describes the emulated flash on the CPU so the mem2flash script can merge flash memory contents with the existing .bit file to produce a new CPU image without rebuilding everything.


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