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Al Williams

Dr. Dobb's Bloggers

On the Bench

March 24, 2014

I enjoy creating FPGA designs, mostly in Verilog. What I don't enjoy is writing repetitive test benches for the little subcomponents that I use in a larger design. If you haven't done much FPGA development, a test bench is just a program that exercises your simulated design and possibly checks for expected outputs.

Writing FPGA "code" in Verilog or VHDL looks like conventional programming, but it isn't. When you describe a circuit in one of these hardware definition languages, you are really writing requirements in a computer-readable language. The tools (analogous to a compiler and a linker) will eventually convert those requirements into hardware on the FPGA. It is customary, though, to simulate the design to get things working before you commit it to the actual hardware.

Because of this, hardware definition languages have a bit of a split personality. A subset of the language is synthesizable — the tools can convert this subset into hardware. The rest of the language can't be synthesized. This part is for writing simulation code like the test bench.

Here's a simple 4-bit parity generator in Verilog:

module par4(input [3:0] bits, output parity);
assign parity=^bits;

The expression ^bits means to exclusive or all of the bits in the input word together. It is a pretty easy bet this will work, but a test bench for this would be pretty simple:

module test;
reg [3:0] testvector;
wire parity;
par4 dut(testvector,parity);  // instantiate device under test

  $dumpfile("dump.vcd");   // output file
  $dumpvars;               // show all variables
// cycle test vector from F to 1
  for (testvector=4'b1111; testvector!=4'b000; testvector--) #1;
// exit simulator
 #10 $finish;

You could run the test using any Verilog simulator like Modelsim or Icarus. However, if you don't have one handy, you can use the very cool cloud-based system provided by EDA Playground. That link will take you to the code and test bench already ready to run. Click on the Open EPWave After Run checkbox and you should see this result:

This is simple enough, but it is a pain when you have lots of small modules and it, frankly, isn't very inspiring. When I used ModelSim, I sometimes used the wave editor to create input vectors and expected outputs. ModelSim can then export the waveform into a testbench. Unfortunately, using open source tools like Icarus and GTKWave (or EDA Playground, which can use ModelSim as a backend, but doesn't provide the wave editor), that's not an option.

If you've read my blog for long, you know I'm pretty lazy about building user interfaces. However, I was thinking that if I had the wave data, it wouldn't be that hard to automatically generate a testbench.

I'll show you my solution next time, but here's a little picture to give you a hint as to my approach:

Before you jump to any conclusions, the spreadsheet is pretty ordinary (although I am using the XWave font). There's no exotic macros or anything. Next time, I'll share the secret.

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